Detecting and managing bad columns

• US 9,348,694 B1
• Filed: 10/09/2013
• Issued: 05/24/2016
• Est. Priority Date: 10/09/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Nassie, Amir
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/050,264
• Time in Patent Office: 958 Days
• Field of Search: 714/718, 714/719, 714/723, 714/773, 714/704, 714/48, 365/200, 365/201, 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A system, computer readable medium and a method. The system includes a memory controller that comprises a control circuit and an interface. The memory controller is arranged to receive or generate bad columns information indicative of bad columns of the NAND flash memory array; wherein the bad columns information has a column resolution. The memory controller is arranged to receive an input data unit to be written to the NAND flash memory array; wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to bad columns of the NAND flash memory array. The interface is arranged to send the input data unit to the NAND flash memory unit; instruct the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit; send the bad column mapped data bits to the NAND flash memory unit; and instruct the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits.

Claims

1. A method for managing bad columns of a NAND flash memory array of a NAND flash memory unit, the method comprises:

receiving or generating bad columns information indicative of the bad columns of the NAND flash memory array on a column to column basis;

receiving an input data unit to be written to the NAND flash memory array;

wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to the bad columns of the NAND flash memory array;

sending the input data unit to the NAND flash memory unit and instructing the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit;

sending the bad column mapped data bits to the NAND flash memory unit; and

instructing the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits; and

wherein the first and second portions of the NAND flash memory array belong to a same physical page of the NAND flash memory array.

2. The method according to claim 1 comprising storing the bad column mapped data bits at a bad column mapped memory unit of a memory controller.

3. The method according to claim 1 comprising detecting the bad column mapped data bits in response to a first data structure that maps the flash memory cells of bad columns to locations of the bad column mapped data bits within the input data unit.

4. The method according to claim 1 comprising storing at the NAND flash memory unit a first data structure that maps the flash memory cells of the bad columns to locations of the bad column mapped data bits and a second data structure that maps codewords to (i) content of the second portion of the NAND flash memory array and to (ii) entries of the first data structure.

5. The method according to claim 1 comprising reading from the first portion of the NAND flash memory unit the programmed input data unit to provide a read data unit;

applying an error correction process on the read data unit to provide error correction results; and

determining whether to read the programmed bad column mapped data bits in response to the error correction results.

6. The method according to claim 5 comprising reading the programmed bad column mapped data bits to provide read bad column mapped data bits;

and generating an output data unit in response to the read data unit and the read bad column mapped data bits.

7. The method according to claim 6 wherein the generating comprises replacing bits of the read data unit that were mapped to flash memory units of bad columns by the read bad column mapped data bits.

8. The method according to claim 6, comprising detecting bits of the read data unit that were mapped to flash memory units of bad columns by accessing a first data structure that maps flash memory cells of bad columns to locations of bad column mapped data bits within the input data unit.

9. The method according to claim 6, wherein the read data unit is associated with a certain codeword out of multiple codewords;

wherein the method comprising detecting bits of the read data unit that belong to the certain codeword by accessing a first data structure that maps flash memory cells of bad columns to locations of bad column mapped data bits and by accessing a second data structure that maps codewords to (i) content of the second portion of the NAND flash memory array and to (ii) entries of the first data structure.

10. A non-transitory computer readable medium that stores instructions to be executed by a computer and cause the computer to perform stages comprising:

receiving or generating bad columns information indicative of bad columns of a NAND flash memory array of a NAND flash memory unit on a column to column basis;

receiving an input data unit to be written to the NAND flash memory array;

wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to the bad columns of the NAND flash memory array;

sending the input data unit to the NAND flash memory unit and instructing the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit;

sending the bad column mapped data bits to the NAND flash memory unit;

instructing the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits; and

wherein the first and second portions of the NAND flash memory array belong to a same physical page of the NAND flash memory array.

11. A system, comprising a memory controller that comprises a

control circuit and an interface;

wherein the control circuit is arranged to receive or generate bad columns information indicative of bad columns of the NAND flash memory array on a column to columns basis;

wherein the memory controller is arranged to receive an input data unit to be written to the NAND flash memory array;

wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to the bad columns of the NAND flash memory array;

wherein the interface is arranged to;

send the input data unit to the NAND flash memory unit;

instruct the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit;

send the bad column mapped data bits to the NAND flash memory unit;

instruct the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits; and

wherein the first and second portions of the NAND flash memory array belong to a same physical page of the NAND flash memory array.

12. The system according to claim 11 wherein the control circuit is arranged to store the bad column mapped data bits at a bad column mapped memory unit of the memory controller.

13. The system according to claim 11 wherein the control circuit is arranged to detect the bad column mapped data bits in response to a first data structure that maps the flash memory cells of the bad columns to locations of the bad column mapped data bits within the input data unit.

14. The system according to claim 11 wherein the control circuit is arranged to store at the NAND flash memory unit a first data structure that maps the flash memory cells of the bad columns to locations of the bad column mapped data bits and a second data structure that maps codewords to (i) content of the second portion of the NAND flash memory array and to (ii) entries of the first data structure.

15. The system according to claim 11 wherein the control circuit is arranged to read from the first portion of the NAND flash memory unit the programmed input data unit to provide a read data unit;

apply an error correction process on the read data unit to provide error correction results; and

determine whether to read the programmed bad column mapped data bits in response to the error correction results.

16. The system according to claim 15 wherein the control circuit is arranged to read the programmed bad column mapped data bits to provide read bad column mapped data bits;

and generate an output data unit in response to the read data unit and the read bad column mapped data bits.

17. The system according to claim 16 wherein the control circuit is arranged to the generate the output data unit by replacing bits of the read data unit that were mapped to flash memory units of bad columns by read bad column mapped data bits.

18. The system according to claim 16, wherein the control circuit is arranged to detect bits of the read data unit that were mapped to flash memory units of bad columns by accessing a first data structure that maps flash memory cells of bad columns to locations of bad column mapped data bits within the input data unit.

19. The system according to claim 16, wherein the read data unit is associated with a certain codeword out of multiple codewords;

wherein the control circuit is arranged to detect bits of the read data unit that belong to the certain codeword by accessing a first data structure that maps flash memory cells of bad columns to locations of bad column mapped data bits and by accessing a second data structure that maps codewords to (i) content of the second portion of the NAND flash memory array and to (ii) entries of the first data structure.