Accessing private data about the state of a data processing machine from storage that is publicly accessible

• US 9,348,767 B2
• Filed: 03/06/2012
• Issued: 05/24/2016
• Est. Priority Date: 11/26/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Robinson, Scott H., Espinosa, Gustavo P., Bennett, Steven M.
• Primary Examiner(s): Traore, Fatoumata
• Application Number:
  US13/413,176
• Publication Number:
  US 20130067184A1
• Time in Patent Office: 1,540 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00

Abstract

According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Claims

1. A processor comprising:

a storage element to store implementation-specific processor private-state data about an active task of the processor;

encryption logic to encode said processor private-state data prior to storage in a publicly accessible private-state location;

wherein the encryption logic comprises;

an address generation unit (AGU) to receive a micro-operation instruction for writing said processor private-state data, and compute an address based upon the instruction;

an address encoding unit to translate said address to point to said publicly accessible location; and

decryption logic to decode said encoded processor private-state data after said encoded processor private-state data has been read from the publicly accessible location; and

processor private-state data decoding hardware to decode said processor private-state data in response to an instruction for accessing the processor private-state data.

2. The processor of claim 1 wherein the decryption logic comprises:

an address decoding unit to translate back said translated address.

3. The processor of claim 1 further comprising:

a first cache to store said encoded processor private-state data; and

a second cache to store said decoded processor private-state data.