Programmable device using fixed and configurable logic to implement floating-point rounding

• US 9,348,795 B1
• Filed: 07/03/2013
• Issued: 05/24/2016
• Est. Priority Date: 07/03/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US13/934,421
• Time in Patent Office: 1,056 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/499 Denomination or exception handling, e.g. rounding or overflow
• CPC Class Codes: G06F 7/49947 Rounding

Abstract

A configurable specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the configurable specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be configurable to route a plurality of block inputs to inputs of the first floating-point arithmetic operator stage, at least one of the block inputs to an input of the second floating-point arithmetic operator stage, output of the first floating-point arithmetic operator stage to an input of the second floating-point arithmetic operator stage, at least one of the block inputs to a direct-connect output to another such block, output of the first floating-point arithmetic operator stage to the direct-connect output, and a direct-connect input from another such block to an input of the second floating-point arithmetic operator stage.

Claims

1. A configurable specialized processing block on an integrated circuit device, said configurable specialized processing block comprising:

a first floating-point arithmetic operator stage;

a second floating-point arithmetic operator stage;

configurable interconnect within said configurable specialized processing block for routing signals into and out of each of said first and second floating-point arithmetic operator stages; and

fixed rounding circuitry for performing a partial rounding operation on output of said second floating-point arithmetic operator stage, said fixed rounding circuitry comprising a rounding condition detector and an overflow detector, said overflow detector comprising;

a first AND-gate combining output mantissa bits of said second floating-point arithmetic operator stage, and

a second AND-gate combining output of said first AND-gate and output of said rounding condition detector.

2. The configurable specialized processing block of claim 1 wherein said rounding condition detector comprises:

circuitry that examines, for presence of at least one ‘

1’

, both (a) a least-significant output mantissa bit of said second floating-point arithmetic operator stage, and (b) output bits of lesser significance of said second floating-point arithmetic operator stage.

3. The configurable specialized processing block of claim 1 wherein said fixed rounding circuitry further comprises an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage.

4. The configurable specialized processing block of claim 3 wherein said fixed rounding circuitry further comprises:

exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage;

or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

5. A programmable integrated circuit device configured for floating-point arithmetic operations, said configured programmable integrated circuit device comprising:

general-purpose programmable logic circuitry; and

a plurality of configurable specialized processing blocks, each of said configurable specialized processing blocks comprising;

a first floating-point arithmetic operator stage,

a second floating-point arithmetic operator stage,

configurable interconnect within said configurable specialized processing block for routing signals into and out of each of said first and second floating-point arithmetic operator stages, and

fixed rounding circuitry for performing a first partial rounding operation on output of said second floating-point arithmetic operator stage, said fixed rounding circuitry comprising a rounding condition detector and an overflow detector, said overflow detector comprising;

a first AND-gate combining output mantissa bits of said second floating-point arithmetic operator stage, and

a second AND-gate combining output of said first AND-gate and output of said rounding condition detector;

wherein;

a portion of said general-purpose programmable logic is configured as additional rounding circuitry for performing a further partial rounding operation on output of said fixed rounding circuitry of at least one of said plurality of configurable specialized processing blocks.

6. The configured programmable integrated circuit device of claim 5 wherein said rounding condition detector comprises:

circuitry that examines, for presence of at least one ‘

1’

, both (a) a least-significant output mantissa bit of said second floating-point arithmetic operator stage, and (b) output bits of lesser significance of said second floating-point arithmetic operator stage.

7. The configured programmable integrated circuit device of claim 5 wherein said portion of said general-purpose programmable logic configured as additional rounding circuitry comprises, for at least one of said configurable specialized processing blocks:

a mantissa adder adding output mantissa bits of said second floating-point arithmetic operator stage to output of said rounding condition detector;

an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

8. The configured programmable integrated circuit device of claim 5 wherein:

for at least one of said configurable specialized processing blocks, said fixed rounding circuitry further comprises an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

said portion of said general-purpose programmable logic configured as additional rounding circuitry comprises, for said at least one of said configurable specialized processing blocks;

a mantissa adder adding output mantissa bits of said second floating-point arithmetic operator stage to output of said rounding condition detector; and

exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

9. The configured programmable integrated circuit device of claim 5 wherein:

for at least one of said configurable specialized processing blocks, said fixed rounding circuitry further comprises an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage, and

exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage; and

said portion of said general-purpose programmable logic configured as additional rounding circuitry comprises, for said at least one of said configurable specialized processing blocks;

a mantissa adder adding output mantissa bits of said second floating-point arithmetic operator stage to output of said rounding condition detector.

10. A method of configuring a programmable integrated circuit device for floating-point arithmetic operations, said programmable integrated circuit device comprising general-purpose programmable logic and a plurality of configurable specialized processing blocks, each of said configurable specialized processing blocks including:

a first floating-point arithmetic operator stage,

a second floating-point arithmetic operator stage,

configurable interconnect within said configurable specialized processing block for routing signals into and out of each of said first and second floating-point arithmetic operator stages, and

fixed rounding circuitry for performing a first partial rounding operation on output of said second floating-point arithmetic operator stage, wherein, in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises;

(a) a rounding condition detector and an overflow detector, or

(b) a rounding condition detector, an overflow detector, and an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage, or

(c) a rounding condition detector, an overflow detector, an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage, and exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage;

said method comprising;

configuring said configurable interconnect to route output of said second floating-point arithmetic operator stage to said fixed rounding circuitry; and

configuring a portion of said general-purpose programmable logic as additional rounding circuitry for performing a further partial rounding operation on output of said fixed rounding circuitry of at least one of said plurality of configurable specialized processing blocks, including, for said at least one of said configurable specialized processing blocks;

configuring a mantissa adder adding output mantissa bits of said second floating-point arithmetic operator stage to output of said rounding condition detector.

11. The method of claim 10 wherein:

in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises said rounding condition detector, and said overflow detector; and

said configuring said portion of said general-purpose programmable logic as additional rounding circuitry further comprises, for said at least one of said configurable specialized processing blocks;

configuring an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

configuring exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

12. The method of claim 10 wherein:

in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises said rounding condition detector, said overflow detector, and said exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

said configuring said portion of said general-purpose programmable logic as additional rounding circuitry further comprises, for said at least one of said configurable specialized processing blocks;

configuring exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

13. A non-transitory data storage medium encoded with machine-executable instructions for performing a method of configuring a programmable integrated circuit device for floating-point arithmetic operations, said programmable integrated circuit device comprising general-purpose programmable logic and a plurality of configurable specialized processing blocks, each of said configurable specialized processing blocks including:

a first floating-point arithmetic operator stage,

a second floating-point arithmetic operator stage,

configurable interconnect within said configurable specialized processing block for routing signals into and out of each of said first and second floating-point arithmetic operator stages, and

fixed rounding circuitry for performing a first partial rounding operation on output of said second floating-point arithmetic operator stage, wherein, in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises;

(a) a rounding condition detector and an overflow detector, or

(b) a rounding condition detector, an overflow detector, and an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage, or

(c) a rounding condition detector, an overflow detector, an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage, and exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage;

said instructions comprising;

instructions to configure said configurable interconnect to route output of said second floating-point arithmetic operator stage to said fixed rounding circuitry; and

instructions to configure a portion of said general-purpose programmable logic as additional rounding circuitry for performing a further partial rounding operation on output of said fixed rounding circuitry of at least one of said plurality of configurable specialized processing blocks, including, for said at least one of said configurable specialized processing blocks;

instructions to configure a mantissa adder adding output mantissa bits of said second floating-point arithmetic operator stage to output of said rounding condition detector.

14. The non-transitory data storage medium of claim 13 wherein:

in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises said rounding condition detector, and said overflow detector; and

said instructions to configure said portion of said general-purpose programmable logic as additional rounding circuitry further comprise, for at least one of said configurable specialized processing blocks;

instructions to configure an exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

instructions to configure exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.

15. The non-transitory data storage medium of claim 13 wherein:

in at least one of said configurable specialized processing blocks, said fixed rounding circuitry comprises said rounding condition detector, said overflow detector, and said exponent adder adding output of said overflow detector to output exponent bits of said second floating-point arithmetic operator stage; and

said instructions to configure said portion of said general-purpose programmable logic as additional rounding circuitry further comprise, for said at least one of said configurable specialized processing blocks;

instructions to configure exception handling circuitry for determining when output of said second floating-point arithmetic operator stage is one of;

a number having an absolute value larger than can be represented by said second floating-point arithmetic operator stage, or

a number smaller than can be represented by said second floating-point arithmetic operator stage.