Boundary word line operation in nonvolatile memory

• US 9,349,479 B1
• Filed: 11/18/2014
• Issued: 05/24/2016
• Est. Priority Date: 11/18/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sehgal, Rohit, Yang, Niles, Kashyap, Abhilash
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/546,591
• Publication Number:
  US 20160141047A1
• Time in Patent Office: 553 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.09, 365/185.11, 365/185.12, 365/185.17, 365/185.18, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.

Claims

1. A nonvolatile memory system comprising:

a plurality of Multi Level Cell (MLC) blocks that store more than one bit per cell;

an identifying circuit that is configured to identify one or more high risk word lines in an individual MLC block that contains data that is at high risk of read disturb errors;

a copying circuit that is configured to selectively copy the data from the one or more high risk word lines to a location outside the individual MLC block; and

a read circuit that is configured to read the data from the location outside the individual MLC block.

2. The nonvolatile memory system of claim 1 further comprising a plurality of Single Level Cell (SLC) blocks that store only one bit per cell, and wherein the location is in an SLC block.

3. The nonvolatile memory system of claim 1 wherein the identifying circuit is configured to identify a boundary between written and unwritten word lines.

4. The nonvolatile memory system of claim 3 further comprising a read count circuit that counts the number of read operations performed on an individual written word line adjacent to the boundary between written and unwritten word lines.

5. The nonvolatile memory system of claim 4 further comprising a comparison circuit in communication with the read count circuit, the comparison circuit configured to compare the number of read operations performed with a threshold number and to designate the individual written word line as a high risk word line if the number of read operations performed exceeds the threshold number.

6. The nonvolatile memory system of claim 1 wherein the identifying circuit is configured to identify the one or more high risk word lines from their physical location at an end of the block.

7. The nonvolatile memory system of claim 6 wherein the MLC blocks are formed in a three dimensional memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, the one or more high risk word lines located in a highest or lowest physical level.

8. A method of operating a nonvolatile memory comprising:

identifying one or more high risk word lines in a Multi Level Cell (MLC) block that contain data that is at high risk of read disturb errors;

selectively copying the data from the one or more high risk word lines to a location outside the MLC block;

maintaining a copy of the data outside the MLC block; and

subsequently directing read requests for the data to the copy of the data outside the MLC block.

9. The method of claim 8 wherein the location outside the MLC block is in a Single Level Cell (SLC) block.

10. The method of claim 8 wherein the identifying one or more high risk word lines is based on proximity to a boundary between written and unwritten word lines.

11. The method of claim 10 wherein the identifying one or more high risk word lines is further based on counting a number of read operations performed on an individual written word line in close proximity to the boundary.

12. The method of claim 11 wherein the individual word line is identified as a high risk word line in response to determining that the number of read operations directed to the individual written word line exceeds a threshold number.

13. The method of claim 8 wherein the identifying one or more high risk word lines is based on physical locations of word lines within a block.

14. The method of claim 13 wherein a word line located at a physical edge of the MLC block is identified as a high risk word line.

15. The method of claim 14 wherein the MLC block is written in a predetermined word line order and the word line at the physical end is the last written word line in the predetermined word line order.

16. The method of claim 14 wherein the nonvolatile memory is a three-dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and wherein the one or more high risk word lines are in a highest or lowest physical level.

17. A method of operating a nonvolatile memory comprising:

writing Multi Level Cell (MLC) data in an MLC block in a plurality of word lines of a block, leaving additional word lines unwritten;

subsequently maintaining a count of read operations performed on a last fully written word line of the block;

comparing the count with a threshold number;

in response to determining that the count exceeds the threshold number, copying the data from the last fully written word line to a Single Level Cell (SLC) block;

maintaining a copy of the data in the SLC block; and

subsequently directing read requests for the data to the copy of the data in the SLC block.

18. The method of claim 17 wherein a partially written word line with only lower page data is located between the last fully written word line and the additional word lines that are unwritten.

19. The method of claim 17 wherein the nonvolatile memory is a three dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.

20. The method of claim 17 wherein the memory system maintains a number of open MLC blocks that are open for writing new data and wherein individual counts are maintained of read operations performed on last fully written word lines of each open MLC block.

21. The method of claim 17 further comprising;

subsequently copying the MLC data from the MLC block to another MLC block and designating the copy of the data in the SLC block as obsolete.

22. The method of claim 21 further comprising, prior to copying the MLC data from the MLC block to another block, writing additional MLC data in the MLC block.

23. The method of claim 22 wherein the writing of the additional MLC data in the MLC block substantially fills the MLC block.