Nonvolatile memory device and operating method thereof

• US 9,349,482 B2
• Filed: 03/05/2015
• Issued: 05/24/2016
• Est. Priority Date: 07/23/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ji-Suk, Park, Il Han, Song, Jung-Ho
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/639,331
• Publication Number:
  US 20160027525A1
• Time in Patent Office: 446 Days
• Field of Search: 365/185.12, 365/185.17, 365/185.18, 365/185.2, 365/185.21, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.

Claims

1. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells;

a page buffer block including page buffers connected to a plurality of bit lines connected with the plurality of memory cells, respectively; and

control logic configured to apply a program voltage to selected ones of the plurality of memory cells, apply a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied, control the page buffers such that a sensing operation is performed with respect to memory cells to which the selected verification voltage is applied, and control the page buffers referring to the sensing result and target state data such that memory cells programmed to a target state are selected.

2. The nonvolatile memory device of claim 1, wherein each of the page buffers includes:

a plurality of data latches configured to store state data corresponding to a state to be programmed at a program operation;

a cache latch configured to receive program data from an external device to transfer the input program data to the plurality of data latches, at the program operation;

a pre-charge circuit configured to apply a pre-charge voltage to the bit lines, before the sensing operation; and

a sense latch configured to store sensing data by latching a voltage of a bit line according to the sensing operation.

3. The nonvolatile memory device of claim 2, wherein the control logic is further configured to select the target state by dumping at least one bit of data stored in the data latches into the sense latch.

4. The nonvolatile memory device of claim 3, wherein the state data is reordered into the form of a sequential binary code under a control of the control logic.

5. The nonvolatile memory device of claim 3, wherein the memory cell array is a three-dimensional memory array.

6. A method of programming a nonvolatile memory device, the method comprising:

applying a program voltage to selected ones of a plurality of memory cells;

applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied;

sensing the memory cells to which the selected verification voltage is applied;

selecting memory cells programmed to a target state referring to the sensing result and target state data; and

determining whether programming of the selected memory cells is passed or failed.

7. The method of claim 6, wherein the selecting includes:

excluding upper states having a threshold voltage higher than the target state by dumping at least one bit of state data stored in data latches, at a sense latch.

8. The method of claim 7, further comprising:

dumping the data latches with a reference data bit such that the target memory cells are inhibited.

9. The method of claim 8, wherein the state data is set according to an ordering with the form of a sequential binary code.

10. The programming method of claim 8, further comprising:

initializing a value of the sense latch before the pre-charging.

11. The method of claim 8, wherein the data latches are dumped with the reference data bit such that memory cells programmed to a threshold voltage lower than the target state and sensed to be an off-cell are inhibited.

12. The method of claim 8, wherein at least one bit of the state data is dumped into the sense latch such that memory cells which is programmed to a threshold voltage higher than the target state but of which the programming is not completed are not inhibited.

13. The method of claim 8, wherein an ordering of state data in the programming is different from that of state data provided as a default value.

14. The method of claim 13, further comprising:

reordering the state data provided as the default value into the form of the sequential binary code before the programming.

15. The method of claim 8, wherein an ordering of state data in the programming is equal to that of state data provided as a default value.

16. A method of programming a nonvolatile memory device which includes a plurality of page buffers, each of which has a sense latch and a plurality of data latches, the method comprising:

applying a program voltage to selected ones of a plurality of memory cells;

applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied;

sensing the memory cells to which the selected verification voltage is applied;

selecting memory cells programmed to a target state referring to the sensing result stored in the sense latch and target state data; and

determining whether programming of the selected memory cells is passed or failed, based on the sensing result.

17. The method of claim 16, wherein the selecting includes:

excluding upper states having a threshold voltage higher than the target state by dumping at least one bit of state data stored in data latches, at a sense latch.

18. The method of claim 17, further comprising:

dumping the data latches with a reference data bit such that the target memory cells are inhibited.

19. The method of claim 18, wherein the state data is binary code that is arranged in an ascending order or a descending order.

20. The method of claim 19, wherein the data latches are dumped with the reference data bit such that memory cells programmed to a threshold voltage lower than the target state and sensed to be an off-cell are inhibited.