Stackable semiconductor package and manufacturing method thereof

• US 9,349,611 B2
• Filed: 02/25/2013
• Issued: 05/24/2016
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Chia-Ching, Ding, Yi-Chuan
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US13/776,567
• Publication Number:
  US 20130171774A1
• Time in Patent Office: 1,184 Days
• Field of Search: 438/121
• US Class Current: 1/1
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05173 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05193 with a principal constituent of the material being a solid not provided for in groups H01L2224/051 - H01L2224/05191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16165 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/21 : of an individual HDI interconnect
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Claims

1. A manufacturing method, comprising:

providing a carrier;

disposing a semiconductor device over the carrier such that an active surface of the semiconductor device faces the carrier, wherein the semiconductor device includes a pad adjacent to the active surface;

forming a package body over the carrier and the semiconductor device, wherein the package body includes a first package surface and a second package surface opposite to the first package surface, and the first package surface faces the carrier;

forming a through-hole in the package body, wherein the through-hole extends between the first package surface and the second package surface;

separating the carrier from the package body;

forming a dielectric layer adjacent to the first package surface, wherein the dielectric layer exposes the pad and the through-hole;

forming a conductive via in the through-hole, wherein the conductive via includes a first end, adjacent to the first package surface, and a second end, adjacent to the second package surface;

forming a patterned conductive layer adjacent to the dielectric layer, wherein the patterned conductive layer is electrically connected to at least one of the pad and the first end of the conductive via; and

forming a stud bump adjacent to the second end of the conductive via.

2. The manufacturing method of claim 1, wherein forming the stud bump is carried out using a wiring tool.

3. The manufacturing method of claim 1, wherein the stud bump is one of a gold stud bump, an aluminum stud bump, and a copper stud bump.

4. The manufacturing method of claim 1, wherein forming the conductive via and forming the patterned conductive layer are carried out substantially simultaneously.

5. The manufacturing method of claim 1, wherein the patterned conductive layer is a first patterned conductive layer, and further comprising:

forming a second patterned conductive layer adjacent to the second package surface, wherein the second patterned conductive layer is electrically connected to the second end of the conductive via and the stud bump.

6. The manufacturing method of claim 5, wherein forming the stud bump is such that the stud bump is laterally displaced from the conductive via.

7. The manufacturing method of claim 6, wherein forming the stud bump is such that the stud bump is inwardly disposed with respect to the conductive via.

8. A manufacturing method, comprising:

providing a package structure including;

providing a package body comprising a semiconductor device including an active surface and a pad adjacent to the active surface, wherein the pad of the semiconductor device is exposed adjacent to a lower surface of the package body,

creating a through hole extending between the lower surface of the package body and an upper surface of the package body,

filling the through hole with a conductive via, and

forming an upper patterned conductive layer adjacent to the upper surface of the package body and electrically connected to an upper end of the conductive via; and

forming a stud bump over the upper patterned conductive layer, wherein the stud bump is laterally displaced from the conductive via.

9. The manufacturing method of claim 8, wherein forming the stud bump is such that the stud bump includes a base portion and a protruded neck portion.

10. The manufacturing method of claim 8, wherein forming the stud bump is such that the stud bump is inwardly disposed with respect to the conductive via.

11. The manufacturing method of claim 8, wherein forming the stud bump is such that the stud bump is disposed outwardly of the side surface of the semiconductor device.

12. The manufacturing method of claim 8, wherein providing the package structure is such that the package structure further includes a lower patterned conductive layer adjacent to the lower package surface and electrically connected to the pad of the semiconductor device and a lower end of the conductive via.

13. The manufacturing method of claim 8, wherein the pad is a first pad, and further comprising:

providing a semiconductor element including a second pad; and

bonding the stud bump to the second pad to form a stacked package assembly.

14. The manufacturing method of claim 13, wherein bonding the stud bump to the second pad is carried out by applying a temperature lower than a reflow temperature.

15. The manufacturing method of claim 8, wherein the stud bump is a first stud bump, and further comprising:

providing a semiconductor element including a second stud bump; and

bonding the first stud bump to the second stud bump to form a stacked package assembly.

16. The manufacturing method of claim 15, wherein bonding the first stud bump to the second stud bump is carried out by applying a temperature lower than a reflow temperature.

17. The manufacturing method of claim 15, wherein bonding the first stud bump to the second stud bump is carried out by applying ultrasonic energy.

18. A manufacturing method, comprising:

providing a package structure including;

a semiconductor device including a pad,

a package body encapsulating the semiconductor device with the pad exposed adjacent to a lower surface of the package body,

a conductive structure at least partially extending between the lower surface of the package body and an upper surface of the package body,

an upper patterned conductive layer extending from an upper end of the conductive structure and along the upper surface of the package body, and

a lower patterned conductive layer extending from a lower end of the conductive structure and along the lower surface of the package body; and

forming a stacking element over the upper patterned conductive layer, wherein the stacking element includes a base portion and a protruded portion disposed over the base portion, and the stacking element is laterally displaced from the conductive structure.

19. The manufacturing method of claim 18, wherein the stacking element is a stud bump.

20. The manufacturing method of claim 18, wherein forming the stacking element is such that the stacking element is laterally disposed between the semiconductor device and the conductive structure.