Substrate, method of manufacturing substrate, semiconductor device, and electronic apparatus

• US 9,349,673 B2
• Filed: 06/27/2013
• Issued: 05/24/2016
• Est. Priority Date: 07/04/2012
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Yoda, Tsuyoshi
• Primary Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US13/929,218
• Publication Number:
  US 20140008816A1
• Time in Patent Office: 1,062 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/024 Dielectric details, e.g. changing the dielectric material around a transmission line

Abstract

A substrate includes a first insulating layer provided on a base board, a second insulating layer provided on the first insulating layer, a third insulating layer provided on the second insulating layer, a pad electrode provided on the third insulating layer, and a hole formed to penetrate the substrate and reaching the pad electrode. A diameter of the hole in the first insulating layer is larger than a diameter of the hole in the second insulating layer, and the first insulating layer and the second insulating layer are formed using different materials from each other and the second insulating layer and the third insulating layer are formed using different materials from each other.

Claims

1. A substrate comprising:

a base board;

three insulating layers stacked on the base board;

a pad electrode provided on the insulating layer in a location farthest from the base board of the three insulating layers; and

a hole formed to penetrate the base board and the three insulating layers and reaching the pad electrode,

wherein a diameter of the hole in the insulating layer in a location closest to the base board of the three insulating layers is larger than a diameter of the hole in the insulating layer in the location farthest from the base board,

the insulating layer in an intermediate location of the three insulating layers is formed using a metal oxide, and

the insulating layer in the location closest to the base board is formed using a semiconductor oxide or a semiconductor nitride.

2. The substrate according to claim 1, wherein the insulating layer in the intermediate location of the three insulating layers is formed at a slower etching rate in dry etching than that for the insulating layer in the location closest to the base board.