Front side copper post joint structure for temporary bond in TSV application

• US 9,349,699 B2
• Filed: 04/21/2014
• Issued: 05/24/2016
• Est. Priority Date: 12/11/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hon-Lin, Hsiao, Ching-Wen, Hsu, Kuo-Ching, Chen, Chen-Shien
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US14/257,734
• Publication Number:
  US 20140227831A1
• Time in Patent Office: 764 Days
• Field of Search: 257/621, 257/E23.011, 257/737, 438/667, 438/613, 438/614, 438/622
• US Class Current: 1/1
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11823 Immersion coating, e.g. in a solder bath
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13562 : On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/818 : Bonding techniques
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.

Claims

1. A method of forming an integrated circuit structure, the method comprising:

providing a substrate, the substrate having one or more metallization layers thereon and one or more conductive vias extending into the substrate;

forming one or more passivation layers over the one or more metallization layers;

forming a post-passivation interconnect (PPI) over the one or more passivation layers, the PPI comprising a conductive pad;

forming a dielectric buffer layer over at least a portion of the conductive pad;

forming an under-bump-metallurgy (UBM) directly coupled to the conductive pad, the UBM extending over at least a portion of the dielectric buffer layer;

forming a conductive pillar over the UBM;

forming one or more conductive materials over the conductive pillar; and

attaching the substrate to a carrier substrate using an adhesive, the adhesive contacting a sidewall of the conductive pillar and extending between the conductive pillar and an adjacent conductive pillar.

2. The method of claim 1, wherein the adhesive fully fills a gap between the substrate and the carrier substrate.

3. The method of claim 2, wherein the one or more conductive materials comprises a solder material, and further comprising, prior to the attaching, performing a reflow process.

4. The method of claim 1, wherein a combined thickness of the conductive pillar and the one or more conductive materials is between about 25 μ

m and about 60 μ

m.

5. The method of claim 1, wherein the forming one or more conductive materials comprises forming a conductive finish over a top surface and sidewalls of the conductive pillar.

6. The method of claim 1, wherein the forming one or more conductive materials comprises forming a conductive cap layer over the conductive pillar and a solder material over the conductive cap layer.

7. The method of claim 1, wherein the conductive pillar comprises a copper-containing material.

8. The method of claim 1, wherein the forming the UBM and the forming the conductive pillar comprises:

forming a conductive UBM layer over the dielectric buffer layer;

forming a patterned mask over the conductive UBM layer, the patterned mask having an opening;

forming the conductive pillar in the opening over a portion of the UBM layer;

removing the patterned mask; and

removing exposed portions of the UBM layer using the conductive pillar as a mask, remaining portions of the UBM layer forming the UBM.

9. A method of forming an integrated circuit structure comprising:

providing a substrate, the substrate having a post-passivation interconnect (PPI) formed thereon;

forming a conductive pillar in electrical contact with the PPI;

forming one or more conductive materials over the conductive pillar, a combined height of the conductive pillar and the one or more conductive materials being between about 25 μ

m and about 60 μ

m;

forming an adhesive extending along a sidewall of the conductive pillar; and

attaching the substrate to a carrier wafer using the adhesive, the conductive pillar and the adhesive being interposed between the substrate and the carrier wafer.

10. The method of claim 9, wherein the forming one or more conductive materials comprises:

forming a conductive barrier layer over the conductive pillar; and

forming a solder material over the conductive barrier layer.

11. The method of claim 9, wherein the forming the one or more conductive materials comprises forming a conductive finish over a top surface and sidewalls of the conductive pillar.

12. The method of claim 9, further comprising attaching the substrate to a carrier substrate using an adhesive.

13. The method of claim 12, wherein the adhesive fills a gap between the substrate and the carrier substrate.

20. The method of claim 10, further comprising reflowing the solder material.

14. A method of forming an integrated circuit structure comprising:

providing a substrate, the substrate having a plurality of conductive pillars formed thereon and one or more conductive materials over each of the conductive pillars, the plurality of conductive pillars comprising a first conductive pillar and a second conductive pillar; and

attaching the substrate to a carrier substrate using an adhesive, the adhesive filling a gap between the substrate and the carrier substrate, the adhesive being interposed between and extending along sidewalls of the first conductive pillar and the second conductive pillar.

15. The method of claim 14, wherein the providing the one or more conductive materials over the conductive pillar comprises:

forming a conductive barrier layer over the conductive pillar;

forming a solder material over the conductive barrier layer; and

reflowing the solder material.

16. The method of claim 15, wherein the reflowing the solder material is performed prior to the attaching the substrate to the carrier substrate.

17. The method of claim 14, wherein the providing the one or more conductive materials over the conductive pillar comprises forming a conductive finish over a top surface and sidewalls of the conductive pillar.

18. The method of claim 14, wherein a combined thickness of the conductive pillar and the one or more conductive materials is between about 25 μ

m and about 60 μ

m.

19. The method of claim 14, wherein the conductive pillar comprises a copper-containing material.