Semiconductor device and manufacturing method thereof

• US 9,349,752 B2
• Filed: 06/05/2014
• Issued: 05/24/2016
• Est. Priority Date: 01/12/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/296,837
• Publication Number:
  US 20140284599A1
• Time in Patent Office: 719 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors

Abstract

A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over an oxide insulating layer;

a protective layer covering an end portion of the oxide semiconductor layer, wherein the end portion of the oxide semiconductor layer comprises a side surface and a part of a top surface of the oxide semiconductor layer;

a first electrode in contact with a bottom surface of the oxide semiconductor layer;

a second electrode in contact with the top surface of the oxide semiconductor layer;

a gate insulating layer in direct contact with the top surface of the oxide semiconductor layer, the gate insulating layer being over the protective layer; and

a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is a non-single-crystal layer including a c-axis-aligned crystalline region.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the second electrode and between which the pair of second oxide semiconductor regions is sandwiched.

4. The semiconductor device according to claim 3,

wherein the first oxide semiconductor region is a channel region,

wherein the pair of second oxide semiconductor regions is electric-field relaxation regions, and

wherein the pair of third oxide semiconductor regions is a source and a drain region.

5. The semiconductor device according to claim 3, wherein the pair of second oxide semiconductor regions includes at least one element selected from nitrogen, phosphorus, and arsenic at a concentration higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

6. The semiconductor device according to claim 3, wherein the pair of second oxide semiconductor regions includes at least one dopant selected from hydrogen, helium, neon, argon, krypton, and xenon at a concentration higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one element selected from In, Ga, Sn, and Zn.

8. The semiconductor device according to claim 1, wherein the oxide insulating layer is an oxide insulating layer from which part of oxygen is released by heat treatment.

9. The semiconductor device according to claim 1, wherein the oxide insulating layer is an oxide insulating layer containing oxygen at a proportion exceeding a stoichiometric proportion.

10. The semiconductor device according to claim 1, wherein the first electrode is in direct contact with the bottom surface of the oxide semiconductor layer and the second electrode is in direct contact with the top surface of the oxide semiconductor layer.

11. The semiconductor device according to claim 1, wherein the gate insulating layer is in direct contact with top surfaces of the first electrode and the second electrode.

12. The semiconductor device according to claim 1, wherein the first electrode and the second electrode are in direct contact with the protective layer.

13. The semiconductor device according to claim 1,

wherein the first electrode is one of a source electrode and a drain electrode, and

wherein the second electrode is the other of the source electrode and the drain electrode.

14. A semiconductor device comprising:

an oxide semiconductor layer over an oxide insulating layer;

a protective layer in direct contact with an end portion of the oxide semiconductor layer, wherein the end portion of the oxide semiconductor layer comprises a side surface and a part of a top surface of the oxide semiconductor layer;

a first electrode in contact with a bottom surface of the oxide semiconductor layer;

a second electrode in contact with the top surface of the oxide semiconductor layer;

a gate insulating layer in direct contact with the top surface of the oxide semiconductor layer, the gate insulating layer being over the protective layer; and

a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor layer is a non-single-crystal layer including a c-axis-aligned crystalline region.

16. The semiconductor device according to claim 14, wherein the oxide semiconductor layer includes a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the second electrode and between which the pair of second oxide semiconductor regions is sandwiched.

17. The semiconductor device according to claim 16,

wherein the first oxide semiconductor region is a channel region,

wherein the pair of second oxide semiconductor regions is electric-field relaxation regions, and

wherein the pair of third oxide semiconductor regions is a source and a drain region.

18. The semiconductor device according to claim 16, wherein the pair of second oxide semiconductor regions includes at least one element selected from nitrogen, phosphorus, and arsenic at a concentration higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

19. The semiconductor device according to claim 16, wherein the pair of second oxide semiconductor regions includes at least one dopant selected from hydrogen, helium, neon, argon, krypton, and xenon at a concentration higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

20. The semiconductor device according to claim 14, wherein the oxide semiconductor layer includes at least one element selected from In, Ga, Sn, and Zn.

21. The semiconductor device according to claim 14, wherein the oxide insulating layer is an oxide insulating layer from which part of oxygen is released by heat treatment.

22. The semiconductor device according to claim 14, wherein the oxide insulating layer is an oxide insulating layer containing oxygen at a proportion exceeding a stoichiometric proportion.

23. The semiconductor device according to claim 14, wherein the first electrode is in direct contact with the bottom surface of the oxide semiconductor layer and the second electrode is in direct contact with the top surface of the oxide semiconductor layer.

24. The semiconductor device according to claim 14, wherein the gate insulating layer is in direct contact with top surfaces of the first electrode and the second electrode.

25. The semiconductor device according to claim 14, wherein the first electrode and the second electrode are in direct contact with the protective layer.

26. The semiconductor device according to claim 14,

wherein the first electrode is one of a source electrode and a drain electrode, and

wherein the second electrode is the other of the source electrode and the drain electrode.