Thin film capacitors embedded in polymer dielectric

• US 9,349,788 B2
• Filed: 08/08/2013
• Issued: 05/24/2016
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
• Inventors: Hurwitz, Dror, Huang, Alex
• Primary Examiner(s): Ha, Nguyen T
• Application Number:
  US13/962,075
• Publication Number:
  US 20150043126A1
• Time in Patent Office: 1,020 Days
• Field of Search: 361/303, 361/305, 3613061-3063, 361311-313, 361/321.2, 361/321.1
• US Class Current: 1/1
• CPC Class Codes: H01G 4/224 Housing; Encapsulation
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H05K 1/162 incorporating printed capacitors

Abstract

A substrate comprising a capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via a via post standing on said capacitor.

Claims

1. A capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via copper contacts, one of said copper contacts being a via post standing on said capacitor.

2. The capacitor of claim 1, wherein at least one electrode comprises a noble metal.

3. The capacitor of claim 2, wherein at least one electrode comprises a noble metal selected from the group comprising tantalum, gold and platinum.

4. The capacitor of claim 1, wherein the dielectric layer is selected from the group consisting of Ta₂O₅, BaO₄SrTi, and TiO₂.

5. The capacitor of claim 1, wherein the dielectric layer further comprises aluminium oxide, such that flaws in the dielectric layer are sealed with aluminium oxide.

6. The capacitor of claim 1, wherein the polymer based encapsulating material is selected from the group consisting of polyimide, epoxy, BT (Bismaleimide/Triazine) and their blends.

7. The capacitor of claim 6, wherein the polymer based encapsulating material further comprises glass fibers.

8. The capacitor of claim 6, wherein the polymer matrix further comprises inorganic particulate fillers having mean particle size of between 0.5 microns and 30 microns and between 15% and 30% of particulate by weight.

9. The capacitor of claim 1 being embedded in a substrate comprising feature layers coupled by via posts laminated with an encapsulating dielectric material.

10. The capacitor of claim 1, being terminated by copper pads separated by solder mask, the copper pads being protected with ENEPIG to prevent tarnish.

11. The capacitor of claim 1, being terminated by copper pads separated by solder mask, the copper pads being protected with an organic varnish to prevent tarnish.

12. A method of fabricating a capacitor comprising the steps of:

(i) Procuring a carrier;

(ii) Depositing a barrier layer;

(iii) Planarizing the barrier layer;

(iv) Depositing a thin layer of copper over the barrier layer;

(v) Depositing a first electrode;

(vi) Depositing a dielectric layer;

(viii) Sputtering a copper seed layer

(ix) Depositing photoresist over the seed layer and patterning the layer of photoresist over the seed layer to create a layer of vias;

(x) Electroplating copper via into the pattern of the photoresist

(xi) Stripping away the photoresist;

(xii) Etching away the seed layer;

(xiv) Laminating dielectric material over the thin film capacitor;

(xv) Thinning and planarizing the dielectric material.

13. The method of claim 12 further comprising an additional step selected from the group consisting of (vb) and (vib) of depositing a layer of aluminium adjacent to the layer of dielectric, and oxidizing to aluminium oxide, thereby sealing defects in the layer of dielectric.

14. The method of claim 13 wherein the first electrode is fabricated from a noble metal.

15. The method of claim 14 wherein the noble metal is selected from the group consisting of gold, platinum and tantalum.

16. The method of claim 12 further comprising an additional step (vii) of depositing a second electrode.

17. The method of claim 16 wherein the second electrode is fabricated from a noble metal selected from the group consisting of gold, platinum and tantalum.

18. The method of claim 16 for fabricating surface mountable capacitors further comprising the steps of:

(xxi) Removing the copper carrier;

(xxii) Removing the barrier layer;

(xxxiii) Depositing a seed layer titanium

(xxiv) Depositing a seed layer of copper

(xxv) Laying down and patterning layers of photoresist on each side of the substrate with embedded capacitor;

(xxvi) Electroplating copper contact ports into the patterned photoresist layers;

(xxvii) Stripping away the patterned photoresist;

(xxviii) Etching away the nickel and copper seed layers leaving discrete copper contact ports;

(xxix) Laying down solder mask around the discrete copper contact ports, and

(xxx) Terminating.

19. The method of claim 18 further comprising the step of singulating.

20. The method of claim 18 wherein said terminating comprises coating the copper contact ports with a tarnish proof conducting layer by ENEPIG.

21. The method of claim 18 wherein said terminating comprises coating the copper contact ports with an organic varnish.

22. The method of claim 12 wherein the dielectric layer is fabricated from a ceramic.

23. The method of claim 22, wherein the ceramic is selected from the group consisting of Ta₂O₅, BaO₄SrTi, and TiO₂.

24. The method of claim 12 further comprising an additional step (xiii) of plasma etching away excess dielectric and electrode material.

25. The method of claim 12 further comprising the steps of:

(xvi) Depositing a further layer of copper over the planarized material;

(xvii) Applying photoresist to both sides of the copper carrier and patterning the upper layer to create an array of capacitors;

(xviii) Etching away exposed areas of the upper layer of copper;

(xix) Removing exposed area of upper electrode, dielectric and lower electrode material;

(xx) Stripping away the photoresist.

26. The method of claim 25 for fabricating surface mountable capacitors further comprising the steps of depositing at least one feature or via layer subsequent to step (xvi).

27. The method of claim 12 for fabricating embedded capacitors further comprising the steps of depositing at least one feature or via layer prior to step (iv).