Semiconductor device having oxide semiconductor channel

• US 9,349,791 B2
• Filed: 04/02/2015
• Issued: 05/24/2016
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takahashi, Kei, Ito, Yoshiaki
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US14/677,180
• Publication Number:
  US 20150279929A1
• Time in Patent Office: 418 Days
• Field of Search: 257/43, 257/64, 257/66, 257/72, 257/E29.068
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.

Claims

1. An integrated circuit comprising a transistor, the transistor comprising:

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer including a channel formation region over the first insulating layer, wherein the channel formation region and the first conductive layer overlap each other with the first insulating layer therebetween,

a second conductive layer in contact with the oxide semiconductor layer;

a third conductive layer in contact with the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer over the second insulating layer, wherein the channel formation region and the fourth conductive layer overlap each other with the second insulating layer therebetween,

wherein the fourth conductive layer overlaps the second conductive layer and the third conductive layer,

wherein the oxide semiconductor layer comprises a first region and a second region below the first region,

wherein the first region comprises a crystal, and a c-axis of the crystal is substantially perpendicular to a surface of the oxide semiconductor layer,

wherein the second region has a lower crystallinity than the first region,

wherein all the metal elements included in the first region are included in the second region, and all the metal elements included in the second region are included in the first region, and

wherein a portion of the second insulating layer is in contact with the first region.

2. The integrated circuit according to claim 1, wherein the second conductive layer and the third conductive layer overlap the first conductive layer.

3. The integrated circuit according to claim 1, wherein the second conductive layer and the third conductive layer are over the oxide semiconductor layer.

4. The integrated circuit according to claim 1, wherein the first region comprises a crystal of In₂Ga₂ZnO₇.

5. The integrated circuit according to claim 1, wherein the oxide semiconductor layer contains an In—

Ga—

Zn—

O-based oxide semiconductor material.

6. The integrated circuit according to claim 1, wherein the second conductive layer and the third conductive layer function as a source electrode and a drain electrode, respectively.

7. The integrated circuit according to claim 1, wherein an upper surface of the oxide semiconductor layer is crystallized.

8. The integrated circuit according to claim 1, wherein the second region includes an amorphous structure.

9. The integrated circuit according to claim 1, wherein the crystal has a size of 20 nm or less.

10. The integrated circuit according to claim 1, wherein the fourth conductive layer functions as a gate electrode.

11. The integrated circuit according to claim 1, wherein the first conductive layer is electrically connected to the fourth conductive layer.

12. The integrated circuit according to claim 1, wherein a potential of the first conductive layer is a floating potential.

13. The integrated circuit according to claim 1, wherein a potential of the first conductive layer is a fixed potential.

14. An inverter comprising a transistor, the transistor comprising:

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer including a channel formation region over the first insulating layer, wherein the channel formation region and the first conductive layer overlap each other with the first insulating layer therebetween,

a second conductive layer in contact with the oxide semiconductor layer;

a third conductive layer in contact with the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer over the second insulating layer, wherein the channel formation region and the fourth conductive layer overlap each other with the second insulating layer therebetween,

wherein the fourth conductive layer overlaps the second conductive layer and the third conductive layer,

wherein the oxide semiconductor layer comprises a first region and a second region below the first region,

wherein the first region comprises a crystal, and a c-axis of the crystal is substantially perpendicular to a surface of the oxide semiconductor layer,

wherein the second region has a lower crystallinity than the first region,

wherein all the metal elements included in the first region are included in the second region, and all the metal elements included in the second region are included in the first region, and

wherein a portion of the second insulating layer is in contact with the first region.

15. The inverter according to claim 14, wherein the second conductive layer and the third conductive layer overlap the first conductive layer.

16. The inverter according to claim 14, wherein the second conductive layer and the third conductive layer are over the oxide semiconductor layer.

17. The inverter according to claim 14, wherein the first region comprises a crystal of In₂Ga₂ZnO₇.

18. The inverter according to claim 14, wherein the oxide semiconductor layer contains an In—

Ga—

Zn—

O-based oxide semiconductor material.

19. The inverter according to claim 14, wherein the second conductive layer and the third conductive layer function as a source electrode and a drain electrode, respectively.

20. The inverter according to claim 14, wherein an upper surface of the oxide semiconductor layer is crystallized.

21. The inverter according to claim 14, wherein the second region includes an amorphous structure.

22. The inverter according to claim 14, wherein the crystal has a size of 20 nm or less.

23. The inverter according to claim 14, wherein the fourth conductive layer functions as a gate electrode.

24. The inverter according to claim 14, wherein the first conductive layer is electrically connected to the fourth conductive layer.

25. The inverter according to claim 14, wherein a potential of the first conductive layer is a floating potential.

26. The inverter according to claim 14, wherein a potential of the first conductive layer is a fixed potential.