Semiconductor structure with airgap

• US 9,349,793 B2
• Filed: 09/08/2014
• Issued: 05/24/2016
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jaffe, Mark D., Joseph, Alvin J., Liu, Qizhi, Stamper, Anthony K.
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US14/480,215
• Publication Number:
  US 20160071925A1
• Time in Patent Office: 624 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78666 : with normal-type structure, e.g. with top gate

Abstract

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Claims

1. A method, comprising:

forming an amorphous layer at a predetermined depth of a substrate;

forming an airgap in the substrate under the amorphous layer; and

forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

2. The method of claim 1, wherein the amorphous layer is formed by an ion implantation process, prior to the formation of the transistor.

3. The method of claim 2, wherein the formation of the amorphous layer comprises:

forming a resist on the substrate;

patterning the resist to form an opening over the active region; and

performing the ion implantation process through the opening, prior to the formation of the transistor and airgap.

4. The method of claim 3, wherein the formation of the airgap comprises:

etching the substrate with NH₄OH to form a trench and an undercut extending laterally below the active region; and

filling the trench with a material,

wherein the amorphous layer is an etch stop layer for the etching of the substrate.

5. The method of claim 4, wherein the material is poly material deposited within the trench.

6. The method of claim 2, further comprising forming another amorphous layer on a bottom surface of the airgap.

7. The method of claim 2, further comprising forming a perimeter of amorphous material surrounding the active region of the transistor.

8. The method of claim 2, wherein the ion implantation process comprises ion implanting species of Ge or Ar.

9. The method of claim 2, further comprising oxidizing a bottom surface of a lateral undercut to form an amorphous layer on a bottom surface of the airgap opposing the amorphous material.

10. The method of claim 9, wherein the oxidizing is a thermal growth process.

11. The method of claim 9, wherein the transistor is bounded by STI structures and the amorphous layer.

12. A method, comprising:

forming at least one deep trench structure in a bulk substrate, on sides of an active region;

forming sidewall structures on sidewalls of the at least one deep trench structure, which acts as an etch stop layer;

forming a lateral undercut in the bulk substrate starting at a bottom of the at least one deep trench structure; and

filling the at least one deep trench structure with material to form an airgap from the lateral undercut in the bulk substrate under the active region,

wherein the lateral undercut is formed by etching with XeF₂.

13. A structure, comprising:

an amorphous layer under an active region of a substrate;

an airgap in the substrate under the amorphous layer; and

a completely isolated transistor in the active region, above the amorphous layer and the airgap and surrounded by shallow trench isolation regions.

14. The structure of claim 13, wherein the substrate is bulk silicon.

15. The structure of claim 13, wherein diffusion regions of the transistor are formed above the amorphous layer and which are abutting the shallow trench isolation regions abutting the amorphous layer.

16. The structure of claim 13, wherein the amorphous layer is ion implanted substrate material.