Method for manufacturing semiconductor device

• US 9,349,820 B2
• Filed: 06/23/2015
• Issued: 05/24/2016
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ichijo, Mitsuhiro, Endo, Toshiya, Suzuki, Kunihiko
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/747,262
• Publication Number:
  US 20150295061A1
• Time in Patent Office: 336 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×10²⁰ atoms/cm³ and a fluorine concentration greater than or equal to 1×10²⁰ atoms/cm³ is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode layer over a substrate;

forming an insulating layer over the gate electrode layer; and

forming an oxide semiconductor layer over and in contact with the insulating layer,

wherein the insulating layer is formed using a gas comprising SiF₄, and

wherein a hydrogen concentration in a part of the insulating layer is less than 6×

10²⁰ atoms/cm³ and a fluorine concentration in the part of the insulating layer is greater than 1×

10²¹ atoms/cm³.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the gas further comprises N₂O.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising heating the oxide semiconductor layer in an inert gas at a temperature greater than or equal to 100°

C. and less than or equal to 400°

C.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystallized region.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate comprises a silicon wafer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode layer comprises copper.

8. A method for a manufacturing semiconductor device comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming source and drain electrode layers over and in contact with the oxide semiconductor layer; and

forming an insulating layer over and in contact with the oxide semiconductor layer,

wherein the insulating layer is formed using a gas comprising SiF₄, and

wherein a hydrogen concentration in a part of the insulating layer is less than 6×

10²⁰ atoms/cm³ and a fluorine concentration in the part of the insulating layer is greater than 1×

10²¹ atoms/cm³.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the gas further comprises N₂O.

10. The method for manufacturing a semiconductor device according to claim 8, further comprising heating the oxide semiconductor layer in an inert gas at a temperature greater than or equal to 100°

C. and less than or equal to 400°

C.

11. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

12. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer includes a crystallized region.

13. The method for manufacturing a semiconductor device according to claim 8, wherein the substrate comprises a silicon wafer.

14. The method for manufacturing a semiconductor device according to claim 8, wherein the source and drain electrode layers comprise copper.