Release strategies for making transferable semiconductor structures, devices and device components

• US 9,349,900 B2
• Filed: 04/07/2014
• Issued: 05/24/2016
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Board of Trustees of The University of Illinois
• Original Assignee: Board of Trustees of The University of Illinois
• Inventors: Rogers, John A., Nuzzo, Ralph G., Meitl, Matthew, Ko, Heung Cho, Yoon, Jongseung, Menard, Etienne, Baca, Alfred J.
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US14/246,962
• Publication Number:
  US 20140361409A1
• Time in Patent Office: 778 Days
• US Class Current: 1/1
• CPC Class Codes: B81C 1/0046 using stamping, e.g. imprinting nanoimprinting for making etch masks G03F7/0002
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 31/03046 including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/072 the potential barriers being only of the PN heterojunction type
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 31/184 : the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: H01L 31/1844 : comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: Y02E 10/52 : PV systems with concentrators
• CPC Class Codes: Y02E 10/544 : Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 156/1195 : Delaminating from release surface

Abstract

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Claims

1. A method of making transferable semiconductor structures, said method comprising the steps of:

providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers;

wherein said release layers are positioned between functional layers in said multilayer structure, and at least one functional layer comprises a plurality of semiconductor structures anchored to said multilayer structure by a heterogeneous anchor, a homogeneous anchor, or a heterogeneous and a homogeneous anchor; and

releasing at least a portion of said semiconductor structures from said multilayer structure by separating one or more of said release layers from one or more of said functional layer and separating said plurality of semiconductor structures from said anchors, thereby generating said transferable semiconductor structures.

2. The method of claim 1, wherein said plurality of semiconductor structures comprises a semiconductor device.

3. The method of claim 2, wherein said semiconductor device is selected from the group consisting of:

a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.

4. The method of claim 1, wherein said semiconductor structures comprise a plurality of semiconductor thin films.

5. The method of claim 4, wherein each of said semiconductor thin films is a single crystalline semiconductor layer.

6. The method of claim 4, wherein each of said semiconductor thin films is selected from the group consisting of:

an organic semiconductor layer, an inorganic semiconductor layer, a III-V semiconductor layer; and

a group IV elemental or compound semiconductor.

7. The method of claim 4, wherein said plurality of semiconductor thin films comprise at least two semiconductor thin films having different semiconductor materials or dopants.

8. The method of claim 1, wherein said semiconductor structures comprise a doped semiconductor layer.

9. The method of claim 8, wherein said doped semiconductor layer forms part of a P-N junction.

10. The method of claim 1, wherein said semiconductor structures comprise a solar cell.

11. The method of claim 1, wherein said semiconductor structures comprise material selected from the group consisting of:

Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP.

12. The method of claim 1, wherein said functional layer further comprises a dielectric layer, an electrode or conducting layer.

13. The method of claim 1, wherein each plurality of semiconductor structures has a thickness selected from a range that is greater than 5 nm and less than 50,000 nm.

14. The method of claim 1, wherein said multilayer structure has a functional layer number that is greater than or equal to 2 and less than or equal to 200, and a release layer number that is greater than or equal to 2 and less than or equal to 200.

15. The method of claim 1 further comprising the step of generating said multilayer structure on a substrate, wherein at least one release layer is provided between said functional layers and said substrate.

16. The method of claim 15 further comprising the step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure;

wherein said substrate is reused during said step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure.

17. The method of claim 1, wherein said plurality of semiconductor structures comprise:

III-V semiconductor epilayers, wherein at least two semiconductor epilayers have different semiconductor materials.

18. The method of claim 1, wherein said plurality of semiconductor structures comprise:

a p-doped GaAs top layer;

a low-doped GaAs middle layer; and

an n-doped GaAs lower layer supported by said release layer.

19. The method of claim 17, wherein said release layer comprises Al_0.9Ga_0.1As.

20. The method of claim 1 for making photovoltaics, wherein said semiconductor structures comprise:

a first layer of n-doped GaAs supported by said release layer;

a second layer supported by said first layer, said second layer comprising a back-surface field or Bragg-reflector layer;

a third layer comprising a n-doped GaAs base layer supported by said second layer;

a fourth layer comprising a p-doped GaAs emitter;

a fifth layer comprising a p-doped In_0.49Ga_0.51P passivation layer supported by said fourth layer; and

a sixth layer comprising a p-doped GaAs layer supported by said fifth layer.

21. The method of claim 20, further comprising a buffer layer positioned between said first and second layer, wherein said buffer layer comprises n-doped GaAs.

22. The method of claim 20, wherein said release layer comprises a layer of Al_0.96Ga_0.04As of sufficient thickness to avoid sagging of said multilayer.

23. The method of claim 22, wherein said release layer thickness is greater than or equal to 300 nm and less than or equal to 2500 nm.

24. The method of claim 20, wherein said plurality of functional layers are selected from a range that is greater than or equal to 2 and less than or equal to 200.

25. The method of claim 1, further comprising providing said multilayer structure on a GaAs substrate.

26. The method of claim 25, wherein each functional layer comprises an n-doped GaAs layer and a semi-insulating layer of AIGaAs.

27. The method of claim 26, wherein said release layer is Al_0.96Ga_0.04As.

28. The method of claim 26, wherein the number of said functional layers is greater than or equal to 2 and less than or equal to 200.

29. The method of claim 1, wherein each functional layer comprises 15 stacked layers arranged from a top-most layer 1 to a bottom-most layer 15 supported by said release layer, and said stacked layers comprise:

1 GaAs;

C

2 Al_0.45Ga_0.55As;

C

3 Al_0.5In_0.5P;

Mg

4 Al_0.25Ga_0.25In_0.5P

5 Ga_0.44In_0.56P

6 Al_0.25Ga_0.25In_0.5P

7 Ga_0.44In_0.56P

8 Al_0.25Ga_0.25In_0.5P

9 Ga_0.44In_0.56P

12 Al_0.25Ga_0.25In_0.5P

13 Al_0.5I_0.5P

14 Al_0.45Ga_0.55As;

Te

15 GaAs;

Te.

30. The method of claim 29, wherein said release layer comprises Al_0.96Ga_0.04As and said multilayer structure is supported by a GaAs substrate.

44. The method of claim 1, wherein the releasing step further comprises dry contact printing to separate said plurality of semiconductor structures from said anchors.

45. The method of claim 44, wherein the releasing step further comprises breaking a tether that connects said plurality of semiconductor structures to said anchors.

46. The method of claim 1, wherein said plurality of semiconductor structures are anchored to said multilayer structure by heterogeneous anchors.

47. The method of claim 46, wherein said heterogeneous anchor is made of a material that is different than the functional layer.

48. The method of claim 46, wherein said heterogeneous anchor is defined after the plurality of semiconductor structures are formed.

49. The method of claim 48, wherein said heterogeneous anchor is made of a material that is the same as the functional layer.

50. The method of claim 46, wherein said heterogeneous anchors comprise a resist material.

51. The method of claim 46, wherein the heterogeneous anchor has a rigidity that resists a lift-off force that is not similarly resisted by non-anchored regions.

52. The method of claim 46, wherein the heterogeneous anchor spans from a top-most functional layer through underlying layers to a wafer that supports the multilayer structure.

53. The method of claim 46, wherein the heterogeneous anchor anchors a top functional layer to an underlying functional layer.

54. The method of claim 46, wherein the heterogeneous anchor is made by:

generating one or more recess features by removing material from said multilayer structure; and

depositing or coating said heterogeneous anchor in said one or more recess features.

55. The method of claim 54, wherein said one or more recess features traverses from a top layer of said multilayer structure to a said substrate supporting said multilayer structure, and said heterogeneous anchor anchors each of said functional layers to said substrate that supports said multilayer structure.

56. The method of claim 55, further comprising the step of:

removing said plurality of release layers;

releasing said transferable semiconductor structures;

removing said heterogeneous anchor; and

reusing said substrate by providing a second multilayer structure supported by said substrate and repeating said steps for generating a heterogeneous anchor to anchor each of said functional layers to said substrate.

57. The method of claim 54, wherein said one or more recess features traverses from a first functional layer that is a top functional layer to a second functional layer that is beneath said top functional layer, and said heterogeneous anchor anchors said first functional layer to said second functional layer.

58. The method of claim 54, wherein said depositing or coating step is carried out using a technique selected from the group consisting of:

vapor-phase epitaxy, molecular-beam epitaxy, evaporation deposition, metalorganic chemical vapor deposition, chemical vapor deposition, physical vapor deposition, sputtering deposition, sol-gel coating, electron beam evaporation deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, liquid phase epitaxy, electrochemical deposition, and spin coating.

59. The method of claim 1, wherein said plurality of semiconductor structures are anchored to said multilayer structure by homogeneous anchors.

31. A multi-layer stack system for providing transferable structures, said multi-layer stack system comprising:

a substrate;

a release layer that covers at least a portion of said substrate;

a plurality of functional layers supported by said release layer and said substrate, wherein adjacent functional layers are separated by a release layer positioned between adjacent functional layers;

wherein at least one of said functional layers comprises a plurality of semiconductor structures; and

wherein said semiconductor structures are connected to a heterogeneous anchor, a homogeneous anchor, or a heterogeneous anchor and a homogeneous anchor, to secure said semiconductor structures in said multi-layer stack system.

32. The multi-layer stack system of claim 31, wherein said semiconductor structures comprise a semiconductor thin film.

33. The multi-layer stack of claim 32, wherein said semiconductor thin film is a doped semiconductor layer.

34. The multi-layer stack of claim 31, wherein said plurality of semiconductor structures comprise a semiconductor device.

35. The multi-layer stack of claim 34, wherein said semiconductor device is selected from the group consisting of a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.

36. The multi-layer stack system of claim 31, wherein said semiconductor structures comprise a plurality of semiconductor thin films.

37. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise:

a top layer of p-doped GaAs;

a middle layer of low-doped GaAs; and

and a bottom layer of n-doped GaAs.

38. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise a layer of n-doped GaAs supported by a semi-insulative layer of AlGaAs.

39. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise:

p-doped GaAs, In_0.49Ga_0.51P and a back-surface field or Bragg-reflector layer.

40. The multi-layer stack system of claim 31, wherein said substrate comprises GaAs and said release layer comprises aluminum gallium arsenide.

41. The multi-layer stack system of claim 40, wherein said release layer comprises Al_0.96Ga_0.04As.

42. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films are independently selected from the group consisting of:

GaAs;

InP;

Al_xGa_1-xAs, with x<

0.5;

InGaAlAsP with AlAs≦

50%;

C;

Si;

Ge;

SiC;

SiGe;

Au;

Ag;

Cu;

Pd;

Pt;

InGaAlN;

In_1-yGa_yAs_xP_1-x, x, y≦

0.05; and

Al_xGa_1-xAs, x≧

0.9.

43. The multi-layer stack system of claim 31, wherein said release layer is selected from the group consisting of:

AlGa_1-xAs, where x≧

0.7;

AlSb,

GaSb,

SiO₂;

an organic polymer;

GaAs_1-xN_y, where y<

x<

1;

Si;

InGaAs; and

GaAs.

60. The multi-layer stack system of claim 31, wherein said anchor is said heterogeneous anchor.

61. The multi-layer stack system of claim 60, wherein said heterogeneous anchor is formed from a material that is different than said functional layers.

62. The multi-layer stack system of claim 61, wherein said heterogeneous anchor comprises a resist material.

63. The multi-layer stack system of claim 62, wherein said resist material is silicon nitride.

64. The multi-layer stack system of claim 60, wherein said heterogeneous anchor traverses from a top-most functional layer to said substrate to connect said top-most functional layer to said substrate.

65. The multi-layer stack system of claim 64, wherein after removal of said release layers, said heterogeneous anchors connect said plurality of semiconductor structures to said substrate.

66. The multi-layer stack system of claim 60, wherein said heterogeneous anchor connects a top-most functional layer to an underlying functional layer.

67. The multi-layer stack system of claim 66, wherein after removal of a top-most release layer that separates said top-most functional layer from said underlying functional layer, said heterogeneous anchors connect said plurality of semiconductor structures to said underlying functional layer.

68. The multi-layer stack system of claim 31, wherein said anchor is said homogeneous anchor.

69. The multi-layer stack system of claim 31, wherein each of the functional layers comprises semiconductor structures.