Horizontally oriented and vertically stacked memory cells

• US 9,349,949 B2
• Filed: 04/16/2015
• Issued: 05/24/2016
• Est. Priority Date: 06/22/2010
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Quick, Timothy A., Marsh, Eugene P.
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US14/688,502
• Publication Number:
  US 20150221866A1
• Time in Patent Office: 404 Days
• Field of Search: 257 2- 5, 257/E29.002, 438102-104
• US Class Current: 1/1
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Claims

1. A memory device, comprising:

a memory cell, wherein the memory cell includes;

a first insulator material;

a memory cell material formed on the first insulator material, wherein the memory cell material has a recess formed therein;

a second insulator material formed on the memory cell material;

a first electrode adjacent a first side of the memory cell material; and

a second electrode conformally deposited in the recess and adjacent a second side of the memory cell material.

2. The memory device of claim 1, wherein the memory device includes an additional memory cell vertically stacked on the memory cell, wherein the additional memory cell includes:

a memory cell material having a recess formed therein;

a first electrode adjacent a first side of the memory cell material; and

a second electrode in the recess and adjacent a second side of the memory cell material.

3. The memory device of claim 2, wherein the second insulator material is between the memory cell material of the memory cell and the memory cell material of the additional memory cell.

4. The memory device of claim 1, wherein:

the first electrode is in direct contact with a single first side of the memory cell material; and

the second electrode is in direct contact with a single second side of the memory cell material.

5. The memory device of claim 1, wherein the first side of the memory cell material is opposite the second side of the memory cell material.

6. A memory device, comprising:

at least two vertically stacked memory cells, wherein each of the memory cells include;

a first insulator material;

a memory cell material formed on the first insulator material, wherein the memory cell material has a recess formed therein;

a first electrode adjacent a first side of the memory cell material; and

a second electrode conformally deposited in the recess and adjacent a second side of the memory cell material.

7. The memory device of claim 6, wherein:

the at least two vertically stacked memory cells form a first vertical stack of memory cells; and

the memory device includes a second vertical stack of memory cells, wherein each of the memory cells of the second vertical stack include;

a memory cell material having a recess formed therein;

a first electrode adjacent a first side of the memory cell material; and

a second electrode in the recess and adjacent a second side of the memory cell material.

8. The memory device of claim 7, wherein the memory device includes a third insulator material between the first vertical stack of memory cells and the second vertical stack of memory cells.

9. The memory device of claim 6, wherein the memory cell material is a resistive memory cell material.

10. The memory device of claim 6, wherein the first electrode is an access device contact.

11. The memory device of claim 6, wherein the second electrode is a metal material.

12. The memory device of claim 11, wherein the metal material is a portion of a data line of the memory device.

13. The memory device of claim 6, wherein each of the memory cells are horizontally oriented memory cells.

14. A method of processing a memory device, comprising:

forming a recess in a memory cell material, wherein forming the recess in the memory cell material includes selectively removing a portion of the memory cell material;

forming a first electrode adjacent a first side of the memory cell material; and

forming a second electrode in the recess and adjacent a second side of the memory cell material.

15. The method of claim 14 wherein forming the second electrode in the recess includes conformally depositing the second electrode in the recess.

16. The method of claim 14, wherein the method includes:

forming the memory cell material on a first insulator material; and

forming a second insulator material on the memory cell material.

17. The method of claim 16, wherein the method includes:

forming the memory cell material on the first insulator material in situ; and

forming the second insulator material on the memory cell material in situ.

18. The method of claim 16, wherein the method includes:

forming the memory cell material on the first insulator material using physical vapor deposition; and

forming the second insulator material on the memory cell material using physical vapor deposition.

19. The method of claim 16, wherein the method includes:

forming an additional memory cell material on the second insulator material; and

forming a recess in the additional memory cell material; and

forming an electrode in the recess and adjacent a side of the additional memory cell material.

20. A method of processing a memory device, comprising:

forming a recess in a memory cell material;

forming a first electrode adjacent a first side of the memory cell material; and

forming a second electrode in the recess and adjacent a second side of the memory cell material, wherein forming the second electrode in the recess includes conformally depositing the second electrode in the recess.