High speed latch with over voltage protection and integrated summing nodes

• US 9,350,331 B2
• Filed: 03/14/2014
• Issued: 05/24/2016
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Cyrusian, Sasan
• Primary Examiner(s): Nguyen, Danny
• Application Number:
  US14/210,644
• Publication Number:
  US 20140268450A1
• Time in Patent Office: 802 Days
• Field of Search: 361/91.1, 361 86- 87
• US Class Current: 1/1
• CPC Class Codes: H02H 3/20 responsive to excess voltage
• CPC Class Codes: H02H 7/1252 responsive to overvoltage in input or output, e.g. by load dump
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H02K 5/24 specially adapted for suppression or reduction of noise or vibrations
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A latch includes a current source, an input amplifier, and a latch output circuit. The current source is configured to output a current based on a voltage source. The input amplifier is configured to receive a differential analog input signal including a first differential input and a second differential input and selectively provide the current based on the first differential input and the second differential input. A latch output circuit is configured to selectively output a differential digital output signal including a first differential output and a second differential output. The latch output circuit includes an over voltage protection circuit configured to receive the current output from the input amplifier, receive the voltage source limit, and output a modified differential digital output signal based on a comparison between a voltage corresponding to each of the first differential output and the second differential output and the voltage source limit.

Claims

1. A latch, comprising:

a current source configured to output a current based on a voltage source;

an input amplifier configured to (i) receive a differential analog input signal including a first differential input and a second differential input, and (ii) selectively provide the current output by the current source based on the first differential input and the second differential input; and

a latch output circuit configured to selectively output, based on the current received from the input amplifier and a voltage source limit, a differential digital output signal including a first differential output and a second differential output, wherein the latch output circuit comprises

an over voltage protection circuit configured to (i) receive the current output from the input amplifier, (ii) receive the voltage source limit, (iii) receive feedback of the differential digital output signal as output from the latch output circuit, and (iv) modify the differential digital output signal based on comparisons between

respective voltages of each of the first differential output and the second differential output as output from the latch output circuit and received by the over voltage protection circuit, and

the voltage source limit.

2. The latch of claim 1, wherein the over voltage protection circuit comprises:

a first transistor in communication with (i) the current received from the input amplifier, (ii) the voltage source limit, and (iii) the first differential output; and

a second transistor in communication with (i) the current received from the input amplifier, (ii) the voltage source limit, and (iii) the second differential output.

3. The latch of claim 2, wherein:

if the first differential output is less than the voltage source limit, the first differential output corresponds to the current received from the input amplifier;

if the first differential output is greater than the voltage source limit, the first transistor is configured to limit the first differential output according to the voltage source limit;

if the second differential output is less than the voltage source limit, the second differential output corresponds to the current received from the input amplifier; and

if the second differential output is greater than the voltage source limit, the second transistor is configured to limit the second differential output according to the voltage source limit.

4. The latch of claim 3, wherein:

the first transistor is OFF if the first differential output is less than the voltage source limit; and

the first transistor is ON if the first differential output is greater than the voltage source limit

the second transistor is OFF if the second differential output is less than the voltage source limit; and

the second transistor is ON if the second differential output is greater than the voltage source limit.

5. The latch of claim 2, wherein the over voltage protection circuit further comprises:

a first buffer amplifier in communication with (i) the current received from the input amplifier, and (ii) the first transistor; and

a second buffer amplifier in communication with (i) the current received from the input amplifier, and (ii) the second transistor.

6. The latch of claim 1, wherein the over voltage protection circuit further comprises a feedback circuit configured to provide feedback corresponding to the differential digital output signal.

7. The latch of claim 6, wherein the feedback circuit includes a pair of transistors in a cross-coupled arrangement.

8. The latch of claim 1, further comprising:

a switch circuit connected between an output of a digital-to-analog converter, and (ii) outputs of the input amplifier.

9. A latch, comprising:

a current source configured to output a current based on a voltage source;

an input amplifier configured to (i) receive a differential analog input signal including a first differential input and a second differential input, and (ii) selectively provide the current output by the current source based on the first differential input and the second differential input;

a latch output circuit configured to selectively output, based on the current received from the input amplifier and a voltage source limit, a differential digital output signal including a first differential output and a second differential output, wherein the latch output circuit comprises

an over voltage protection circuit configured to (i) receive the current output from the input amplifier, (ii) receive the voltage source limit, and (iii) modify the differential digital output signal based on comparisons between

respective voltages of each of the first differential output and the second differential output, and

the voltage source limit;

a switch circuit configured to provide an output signal based on an output of a digital-to-analog converter (DAC); and

an integrated summing node arranged between the input amplifier and the latch output circuit, the integrated summing node configured to combine (i) the current provided by the input amplifier and (ii) the output signal provided by the switch circuit.

10. The latch of claim 9, further comprising:

an analog XOR circuit arranged between the DAC and the switch circuit.

11. The latch of claim 10, further comprising a common node circuit connected between (i) a first pair of switches of the switch circuit, and (ii) a second pair of switches of the switch circuit.

12. A method of operating a latch, the method comprising:

outputting, from a current source, a current based on a voltage source;

receiving a differential analog input signal including a first differential input and a second differential input;

selectively providing, from an input amplifier, the current output by the current source based on the first differential input and the second differential input;

selectively outputting from the latch, based on the current received from the input amplifier and a voltage source limit, a differential digital output signal including a first differential output and a second differential output;

receiving feedback of the differential digital output signal as output from the latch; and

modifying the differential digital output signal based on comparisons between

respective voltages of each of the first differential output and the second differential output as output from the latch, and

the voltage source limit.

13. The method of claim 12, wherein:

if the first differential output is less than the voltage source limit, the first differential output corresponds to the current received from the input amplifier;

if the first differential output is greater than the voltage source limit, the first differential output is limited according to the voltage source limit;

if the second differential output is less than the voltage source limit, the second differential output corresponds to the current received from the input amplifier; and

if the second differential output is greater than the voltage source limit, the second differential output is limited according to the voltage source limit.

14. The method of claim 12, further comprising providing feedback corresponding to the differential digital output signal.

15. A method of operating a latch, the method comprising:

outputting, from a current source, a current based on a voltage source;

receiving a differential analog input signal including a first differential input and a second differential input;

selectively providing, from an input amplifier, the current output by the current source based on the first differential input and the second differential input;

selectively outputting, based on the current received from the input amplifier and a voltage source limit, a differential digital output signal including a first differential output and a second differential output;

modifying the differential digital output signal based on comparisons between

respective voltages of each of the first differential output and the second differential output, and

the voltage source limit;

providing an output signal based on an output of a digital-to-analog converter (DAC); and

combining (i) the current provided by the input amplifier and (ii) the output signal.