Systems and methods for clock distribution in a die-to-die interface

• US 9,350,339 B2
• Filed: 07/18/2014
• Issued: 05/24/2016
• Est. Priority Date: 07/18/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Bryan, Thomas Clark, Loke, Alvin Leng Sun, Knol, Stephen, Lynch, Gregory Francis, Wee, Tin Tin, Peterson, LuVerne Ray, Li, Yue
• Primary Examiner(s): Puentes, Daniel
• Application Number:
  US14/335,681
• Publication Number:
  US 20160020759A1
• Time in Patent Office: 676 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 5/15013 with more than two outputs

Abstract

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Claims

1. A multi-die package comprising:

a first die having a transmit clock tree feeding a first plurality of flip-flops; and

a second die having a receive clock tree feeding a second plurality of flip-flops, wherein the transmit clock tree is configured to forward a clock signal to the receive clock tree;

wherein individual flip-flops on the first die have a bit correspondence to respective individual flip-flops on the second die, each clock tree being unbalanced and configured to provide matched insertion delays for corresponding flip-flops on the first and second die, wherein the individual flip-flops of the first plurality of flip-flops have different insertion delays relative to each other, and wherein the individual flip-flops of the second plurality of flip-flops have different insertion delays relative to each other.

2. The multi-die package of claim 1, wherein corresponding flip-flops are connected across the die by data routes, wherein the data routes are the same length.

3. The multi-die package of claim 1, wherein the first plurality of flip-flops and the second plurality of flip-flops are configured to receive a same clock.

4. The multi-die package of claim 1, wherein the transmit clock tree has non-uniform route lengths, and wherein the receive clock tree has non-uniform route lengths.

5. The multi-die package of claim 1, wherein the multi-die package further comprises:

a substrate upon which the first and second die are disposed;

a plurality of metal layers configured to provide electrical communication between the first and second die and with external pins of the package; and

dielectric layers grown over the first and second die.

6. The multi-die package of claim 1, wherein the multi-die package further includes:

an interposer configured to provide electrical communication between the first and second die and with external pins of the package.

7. The multi-die package of claim 1, wherein an insertion delay for a given flip-flop of the first plurality of flip-flops includes a propagation delay from a time the clock signal rises at a start node of the transmit clock tree to a time the clock rises at the given flip flop.

8. The multi-die package of claim 1, wherein an insertion delay for a given flip-flop of the second plurality of flip-flops includes a propagation delay from a time the clock signal rises at a start node of the receive clock tree to a time the clock rises at the given flip flop.

9. A method for providing a clock signal at a die-to-die interface, the method comprising:

at a first clock tree at a first die;

distributing the clock signal to a first plurality of flip-flops, each of the flip-flops of the first plurality transmitting data to a corresponding receive flip-flop in response to the clock signal; and

forwarding the clock to a second clock tree at a second die;

at the second clock tree, wherein each of the corresponding receive flip-flops is in a second plurality of flip-flops;

distributing the clock signal to the second plurality of flip-flops, each of the flip-flops of the second plurality capturing data from a corresponding one of the first plurality of flip-flops in response to the clock signal;

wherein the first clock tree distributes the clock signal with different insertion delays for each of the flip-flops of the first plurality of flip-flops.

10. The method of claim 9, wherein the second clock tree distributes the clock signal with different insertion delays for each of the receive flip-flops of the second plurality of flip-flops.

11. The method of claim 10, wherein an insertion delay at a particular one of the first plurality of flip-flops matches an insertion delay at a corresponding one of the second plurality of flip-flops.

12. The method of claim 9, wherein a given flip-flop of the first plurality of flip-flops and its corresponding flip-flop of the second plurality of flip-flops are associated with a bit.