Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

• US 9,351,899 B2
• Filed: 06/30/2014
• Issued: 05/31/2016
• Est. Priority Date: 01/21/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bose, Pradip, Buyuktosunoglu, Alper, Guo, Xiaochen, Hunter, Hillery C., Rivers, Jude A., Srinivasan, Vijayalakshmi
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/320,219
• Publication Number:
  US 20150206569A1
• Time in Patent Office: 701 Days
• Field of Search: 365/158, 365/80, 365/171, 365/173, 257/421, 257/427
• US Class Current: 1/1
• CPC Class Codes: A61G 5/02 propelled by the patient or disabled person
• CPC Class Codes: A61G 5/1075 tilting the whole seat backwards tilting forwards for standing-up or sitting-down aids A61G5/14
• CPC Class Codes: A61H 2003/004 Trays
• CPC Class Codes: A61H 2201/0161 Size reducing arrangements when not in use, for stowing or transport
• CPC Class Codes: A61H 2201/1633 Seat A61H2201/0149 takes precedence
• CPC Class Codes: A61H 3/00 Appliances for aiding patients or disabled persons to walk about apparatus for helping babies to walk A47D13/04; orthopaedic devices for correcting deformities of, or supporting, limbs A61F5/0102; exercising apparatus for the feet or toes A63B23/10; stairways or ramps E04F11/00
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: Y10T 29/49826 Assembling or joining

Abstract

Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Claims

1. A method of managing memory, the method comprising:

determining a temperature associated with a memory;

in response to determining that the temperature is greater than a latency-determining threshold value, adjusting a programming pulse width based on at least the temperature;

determining a level of write queue utilization associated with the memory; and

in response to determining that the level of write queue utilization is above a high water mark indicator, performing a write operation based on the programming pulse width.

2. The method of claim 1, wherein performing the write operation further comprises initiating a false write operation.

3. The method of claim 1, further comprising halting a false write operation in response to at least one of a detection of a desired temperature, an expiration of a time period, and a memory capacity indication.

4. The method of claim 1, further comprising determining the level of write queue utilization based on the high water mark indicator.

5. The method of claim 4, further comprising determining the level of write queue utilization by comparing the high water mark indicator to a utilization threshold value.

6. The method of claim 4, further comprising incrementing the high water mark indicator in response to a received write request and decrementing the high water mark indicator in response to a write request being written.

7. The method of claim 1, wherein performing the write operation further comprises determining whether the level of write queue utilization is below a programmable utilization threshold value.

8. The method of claim 1, wherein performing the write operation further comprises an adjusted a programming pulse width.

9. The method of claim 1, wherein performing the write operation further comprises determining that the temperature is below the latency-determining threshold value.

10. The method of claim 1, wherein the memory includes a memory write queue.

11. The method of claim 1, wherein the memory includes a spin transfer torque magnetoresistive random-access memory (STT-MRAM).

12. The method of claim 1, wherein determining the temperature further comprises continuously determining the temperature.

13. The method of claim 1, wherein performing the write operation further comprises performing a bulk write operation that services multiple write requests.

14. The method of claim 1, wherein performing the write operation further comprises using a multiplexer configured to receive a first input from the high water mark indicator and a second input from a false write queue.

15. The method of claim 1, wherein the programming pulse width is adjusted further based on at least one of a coding strength of data, an application requirement, or a history based performance parameter associated with past performance of a system.

16. The method of claim 1, further comprising adjusting the programming pulse width based on stored relationship information that is associated with at least one of a bit error rate of the memory, a voltage of the memory, historical data, or coding data.

17. The method of claim 1, further comprising sending a false memory request upon a determination that fewer than a threshold number of real memory requests are received.