Enabling a non-core domain to control memory bandwidth in a processor

• US 9,354,692 B2
• Filed: 08/05/2014
• Issued: 05/31/2016
• Est. Priority Date: 10/27/2011
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Sodhi, Inder M., Rotem, Efraim, Rajwan, Doron, Weissmann, Eliezer, Wells, Ryan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US14/451,807
• Publication Number:
  US 20140344598A1
• Time in Patent Office: 665 Days
• Field of Search: 713300-340
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first domain including at least one core to execute instructions;

a second domain including at least one execution unit to execute instructions transparent to an operating system (OS), wherein a driver of the second domain is to control execution on the second domain;

an interconnect to interconnect the first domain and the second domain to a memory coupled to the processor; and

a power controller to control a frequency of the interconnect based on memory boundedness of a workload executed on the second domain.

2. The processor of claim 1, wherein the driver of the second domain is to request the power controller to update the interconnect frequency based on the memory boundedness.

3. The processor of claim 1, wherein the driver of the second domain is to determine the memory boundedness based on statistics collected during execution of the workload on the second domain.

4. The processor of claim 1, wherein the power controller includes a mapping table to map a frequency of the second domain to a minimum interconnect frequency.

5. The processor of claim 1, wherein the at least one execution unit comprises a plurality of graphics engines.

6. The processor of claim 1, wherein the power controller is to control the first domain and the second domain to operate at different voltage levels.

7. The processor of claim 1, wherein the power controller is to control the first and second domains to dynamically enter into and exit one or more low power states.

8. The processor of claim 1, further comprising a ring interconnect to couple the first domain and the second domain.

9. The processor of claim 2, wherein the interconnect is of the first domain, and the power controller is to update a frequency of the first domain responsive to the second domain driver request.

10. The processor of claim 4, wherein the driver of the second domain is to provide a first set of entries for the mapping table when the processor is enabled, and to update at least some of the first set of entries based on a change to a workload of the second domain.

11. The processor of claim 2, wherein the power controller is to control the interconnect frequency to be a maximum of a frequency requested by the driver of the second domain and a first domain frequency requested by the OS, and to reduce the interconnect frequency to the first domain frequency when the second domain enters a low power mode.

12. The processor of claim 6, further comprising a third domain including the power controller, wherein the third domain is to operate at a fixed frequency.

13. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving a message from a first domain of a multi-domain processor, in a controller of the multi-domain processor, the message including a request to configure a mapping table to store a mapping between a frequency of the first domain and a minimum frequency of an interconnect that couples the first domain to a cache memory of the multi-domain processor;

writing a plurality of entries of the mapping table, each entry including a mapping between a first domain frequency and a minimum interconnect frequency; and

controlling a frequency of the interconnect using the mapping table, responsive to a frequency at which the first domain is operating.

14. The machine-readable medium of claim 13, wherein each of the plurality of entries includes a ratio between a first domain frequency and an interconnect frequency.

15. The machine-readable medium of claim 13, wherein each of the plurality of entries includes a first domain frequency and a corresponding interconnect minimum frequency.

16. The machine-readable medium of claim 13, wherein the method further comprises gathering statistics on memory boundedness of a workload executing on the first domain.

17. The machine-readable medium of claim 13, wherein the method further comprises limiting the interconnect frequency to less than the minimum interconnect frequency for a corresponding frequency at which the first domain is operating when a second domain of the multi-domain processor is thermally or power limited.

18. A system comprising:

a multi-domain processor including a first domain having at least one core and an interconnect, a second domain including at least one execution unit to execute instructions transparently to an operating system, and a third domain, the third domain including a mapping table to map a frequency of the second domain to a minimum frequency of the interconnect, wherein the second domain is to send a request to the third domain to cause an update to the interconnect frequency based at least in part on a workload executed on the second domain; and

a dynamic random access memory (DRAM) coupled to the multi-domain processor.

19. The system of claim 18, wherein a driver of the second domain is to write an indicator and an address into a first register of a mailbox interface of the third domain and to write data into a second register of the mailbox interface, and responsive to the indicator the third domain is to write the data into an entry of the mapping table addressed by the address in the first register.

20. The system of claim 18, wherein the third domain is to control the interconnect frequency to be a maximum of a frequency requested by the driver of the second domain and a first domain frequency requested by the operating system.