System integrator and system integration method with reliability optimized integrated circuit chip selection

• US 9,354,953 B2
• Filed: 07/24/2014
• Issued: 05/31/2016
• Est. Priority Date: 07/24/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bickford, Jeanne P., Habib, Nazmul, Li, Baozhen
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US14/339,854
• Publication Number:
  US 20160026517A1
• Time in Patent Office: 677 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files

Abstract

Disclosed is a computer system for system integration, wherein chip selection for a specific system is performance and reliability optimized and, thereby cost optimized. In the system, a memory stores a chip-level performance specification and a chip-level reliability specifications, each defined for a specific integrated circuit chip that is to be incorporated into a specific system. The memory also stores an inventory that references manufactured instances of the specific integrated circuit chip sorted into bins, which are associated with different performance process windows and which are assigned different reliability levels. A processor uses the inventory to select an instance of the specific integrated circuit chip from one of the bins for actual incorporation into the specific system and does so such that the chip-level performance specification and the chip-level reliability specification are met. Also disclosed are a method and a computer program product that can similarly perform system integration.

Claims

1. A method for system integration, said method comprising:

accessing, by a processor from a memory, a chip-level performance specification, a chip-level reliability specification and an inventory,

said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,

said specific system having a system-level reliability specification,

said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and

said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and

,

selecting, by said processor from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level performance specification and said chip-level reliability specification.

2. The method of claim 1, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.

3. The method of claim 2, further comprising, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, receiving, by said processor, feedback as to an actual number of power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, by said processor for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).

4. The method of claim 1,

each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and

each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.

5. The method of claim 4, said reliability level indicating a minimum number of power on hours (POHs) during which each manufactured instance of said specific integrated circuit chip contained in said bin is expected, with a specified probability, to perform without fail.

6. The method of claim 1, said inventory associating an identifier with each of said bins, said identifier indicating said specific integrated circuit chip, a specific performance process window and a reliability level.

7. The method of claim 1, said different performance process windows comprising different ranges of maximum oscillation frequency.

8. The method of claim 1, further comprising repeating, by said processor, said accessing and said selecting for each additional integrated circuit chip identified for incorporation into said specific system.

9. A computer system for system integration, said computer system comprising:

a memory storing a chip-level performance specification, a chip-level reliability specification and an inventory,

said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,

said specific system having a system-level reliability specification,

said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and

said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and

,

a processor accessing said memory and selecting, from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level reliability specification.

10. The computer system of claim 9, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.

11. The computer system of claim 10, said processor further receiving, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, feedback as to an actual number power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).

12. The computer system of claim 9,

each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and

each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.

13. The computer system of claim 12, said reliability level indicating a minimum number of power on hours (POHs) during which each manufactured instance of said specific integrated circuit chip contained in said bin is expected, with a specified probability, to perform without fail.

14. The computer system of claim 9, said inventory associating an identifier with each of said bins, said identifier indicating said specific integrated circuit chip, a specific performance process window and a reliability level.

15. The computer system of claim 9, said different performance process windows comprising different ranges of maximum oscillation frequency.

16. The computer system of claim 9, said processor further repeating said accessing and said selecting for each additional integrated circuit chip identified for incorporation into said specific system.

17. A computer program product for system integration, said computer program product comprising a computer readable storage medium storing a program instructions, said program instructions being executable by a computer system to cause said computer system to perform a method, said method comprising:

accessing, from a memory, a chip-level performance specification, a chip-level reliability specification and an inventory,

said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,

said specific system having a system-level reliability specification,

said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and

said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and

,

selecting, from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level reliability specification.

18. The computer program product of claim 17, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.

19. The computer program product of claim 18, said method further comprising, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, receiving feedback as to an actual number of power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).

20. The computer program product of claim 17,

each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and

each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.