Vector multiplication with operand base system conversion and re-conversion

• US 9,355,068 B2
• Filed: 06/29/2012
• Issued: 05/31/2016
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay, Krasnov, Vlad
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/538,499
• Publication Number:
  US 20140006469A1
• Time in Patent Office: 1,432 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format

Abstract

A method is described that includes performing the following with an instruction execution pipeline of a semiconductor chip. Multiplying two vectors by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying with a first execution unit of the pipeline the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and, converting contents of the register into the first base system.

Claims

1. A method comprising:

decoding a single instruction with a hardware decoder of a hardware processor; and

executing the single instruction with a hardware execution unit of the hardware processor by;

receiving a vector element multiplicand and vector element multiplier expressed in a first base system;

converting said vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier;

multiplying said converted vector element multiplicand and said converted vector element multiplier to form a multiplication result;

accumulating in a register a portion of said multiplication result with a portion of a result of a prior multiplication of operands expressed in said second lower base system; and

converting contents of said register into said first base system.

2. The method of claim 1 wherein said first base system corresponds to a maximum digit size of 64 bits.

3. The method of claim 2 wherein said second lower base system corresponds to a maximum digit size of 52 bits.

4. The method of claim 1 wherein said contents of said register include a digit that is larger than said second lower base system'"'"'s largest digit.

5. The method of claim 1 wherein the executing further comprises iteratively performing multiplication and accumulation sequences to effect a complete multiplication of two vectors, and said iterative multiplication and accumulation sequences include a broadcast operation that instantiates one element of a multiplier across each of multiple elements of a vector.

6. The method of claim 5 wherein said iterative multiplication and accumulation sequences include a shift operation that shifts elements of a multiplicand to a neighboring vector element location.

7. A hardware processor comprising:

a hardware decoder to decode a single instruction; and

a hardware execution unit to execute the single instruction to;

receive a vector element multiplicand and vector element multiplier expressed in a first base system;

convert said vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier;

multiply said converted vector element multiplicand and said converted vector element multiplier to form a multiplication result;

accumulate in a register a portion of said multiplication result with a portion of a result of a prior multiplication of operands expressed in said second lower base system; and

convert contents of said register into said first base system.

8. The hardware processor of claim 7 wherein said first base system corresponds to a maximum digit size of 64 bits.

9. The hardware processor of claim 8 wherein said second lower base system corresponds to a maximum digit size of 52 bits.

10. The hardware processor of claim 7 wherein said contents of said register include a digit that is larger than said second lower base system'"'"'s largest digit.

11. The hardware processor of claim 7 wherein said hardware execution unit is to execute the single instruction by iteratively performing multiplication and accumulation sequences to effect a complete multiplication of two vectors and said iterative multiplication and accumulation sequences include a broadcast operation that instantiates one element of a multiplier across each of multiple elements of a vector.

12. The hardware processor of claim 11 wherein said iterative multiplication and accumulation sequences include a shift operation that shifts elements of a multiplicand to a neighboring vector element location.