Dual trench isolation for CMOS with hybrid orientations

• US 9,355,887 B2
• Filed: 01/12/2012
• Issued: 05/31/2016
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chan, Victor, Ieong, Meikei, Rengarajan, Rajesh, Reznicek, Alexander, Sung, Chun-yung, Yang, Min
• Primary Examiner(s): Graybill, David E
• Application Number:
  US13/349,203
• Publication Number:
  US 20120104511A1
• Time in Patent Office: 1,601 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Claims

1. A semiconductor structure comprising:

a hybrid oriented substrate comprising a first device region having a first crystallographic orientation and a second device region having a second crystallographic orientation which differs from the first crystallographic orientation;

a first trench isolation region of a first depth separating said first device region from said second device region;

a plurality of second trench isolation regions of a second depth which is shallower than the first depth located in each of said first and second device regions; and

first semiconductor devices of a first polarity located in said first semiconductor device region and second semiconductor devices of a second polarity that differs from the first polarity located in said second semiconductor device region, wherein said first semiconductor devices are separated by said first trench isolation region and said plurality of second trench isolation structures separate said first semiconductor devices or said second semiconductor devices from each other, and wherein said first trench isolation region has a first sidewall comprising an upper portion extending to a topmost surface of said first trench isolation region and directly contacting a second semiconductor layer of said second crystallographic orientation and a lower portion directly contacting a first semiconductor layer of said first crystallographic orientation, and a second sidewall that directly contacts a regrown semiconductor material of said first crystallographic orientation.

2. The semiconductor structure of claim 1 wherein the first crystallographic orientation is (110) and the second crystallographic orientation is (100).

3. The semiconductor structure of claim 2 wherein said first semiconductor devices are pFETs and second semiconductor devices nFETs.

4. The semiconductor structure of claim 1 wherein the first crystallographic orientation is (100) and the second crystallographic orientation is (110).

5. The semiconductor structure of claim 4 wherein said first semiconductor devices are nFETs and the second semiconductor devices are pFETs.

6. The semiconductor structure of claim 1 wherein said regrown semiconductor material is a Si-containing semiconductor.

7. The semiconductor structure of claim 1 wherein said first and second semiconductor layers are separated from each other by a conductive bonding interface.

8. The semiconductor structure of claim 1 wherein said first trench isolation region is a spacer.

9. The semiconductor structure of claim 8 wherein said spacer is a single spacer.

10. The semiconductor structure of claim 8 wherein said spacer comprises multiple spacers.

11. The semiconductor structure of claim 1 wherein said second semiconductor layer and said regrown semiconductor material have topmost surfaces that are coplanar with each other.