Cooling channels in 3DIC stacks

• US 9,355,933 B2
• Filed: 12/18/2013
• Issued: 05/31/2016
• Est. Priority Date: 11/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Hsiao, Ching-Wen, Wang, Tsung-Ding, Tseng, Ming Hung, Chen, Chen-Shien
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US14/132,515
• Publication Number:
  US 20140103540A1
• Time in Patent Office: 895 Days
• Field of Search: 438/629, 438/637, 438/639, 438/109, 438/273, 438/531
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/46 involving the transfer of heat by flowing fluids H01L23/42, H01L23/44 take precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Claims

1. A method comprising:

forming a wafer comprising;

forming a first interconnect structure comprising metal lines and vias in first dielectric layers, wherein the first interconnect structure is on a front side of a first semiconductor substrate;

forming a first plurality of channels with at least a portion in the first dielectric layers; and

laminating a dielectric film over the first interconnect structure and sealing portions of the first plurality of channels, wherein the portions of the first plurality of channels are configured to allow a fluid flowing through.

2. The method of claim 1, wherein the step of forming the first plurality of channels comprises:

forming through-substrate vias (TSVs) in the first semiconductor substrate;

after the step of forming the first interconnect structure, etching the first dielectric layers to form the first plurality of channels in the first interconnect structure; and

removing the TSVs to extend the first plurality of channels into the first semiconductor substrate.

3. The method of claim 2, wherein the step of removing the TSVs is performed after the step of laminating the dielectric film.

4. The method of claim 1, wherein the first plurality of channels comprises:

a first portion routing in a first layer of the first dielectric layers and not in a second layer of the first dielectric layers; and

a second portion routing in the second layer and not in the first layer, wherein the first portion and the second portion are vertically misaligned.

5. The method of claim 1, wherein the forming the first plurality of channels comprises:

during the step of forming the first interconnect structure, forming metal lines and vias in a form of interconnected metal pipes, with materials of the first dielectric layers filling the metal pipes; and

removing the materials of the first dielectric layers in the metal pipes.

6. The method of claim 1 further comprising bonding a second die to a first die in the wafer.

7. The method of claim 6, wherein the second die comprises:

a second semiconductor substrate;

a second interconnect structure comprising metals and vias in second dielectric layers and on a front side of the second semiconductor substrate; and

a second plurality of channels in the second dielectric layers, wherein after the step of bonding the second die to the first die, the first plurality of channels and the second plurality of channels are interconnected.

8. The method of claim 6, wherein the second die comprises no channel connected to the first plurality of channels.

9. The method of claim 1 further comprising attaching a first fluidic tube and a second fluidic tube to an inlet and an outlet of the first plurality of channels, respectively.

10. The method of claim 9 further comprising conducting a cooling agent into the first fluidic tube, wherein the cooling agent flows through the first plurality of channels to the second fluidic tube.

11. A method comprising:

forming a wafer comprising;

providing a first semiconductor substrate;

forming a plurality of through-substrate vias (TSVs) in the first semiconductor substrate;

forming a first interconnect structure comprising metal lines and vias in first dielectric layers and on a front side of the first semiconductor substrate, wherein the metal lines and vias form interconnected metal pipes encircling portions of the first dielectric layers;

removing the portions of the first dielectric layers encircled by the interconnected metal pipes to form a first plurality of channels in the first dielectric layers;

laminating a dielectric film on the first interconnect structure and sealing the first plurality of channels;

polishing a backside of the first semiconductor substrate to expose the plurality of TSVs; and

removing the plurality of TSVs to extend the first plurality of channels into the first semiconductor substrate.

12. The method of claim 11 further comprising attaching a first fluidic tube and a second fluidic tube to a first one and a second one of the first plurality of channels left by the removed TSVs.

13. The method of claim 11, wherein the step of removing the TSVs is performed after the step of laminating the dielectric film.

14. The method of claim 11, wherein the first plurality of channels comprises:

a first portion routing in a first layer of the first dielectric layers and not in a second layer of the first dielectric layers; and

a second portion routing in the second layer and not in the first layer, wherein the first portion and the second portion are not vertically overlapped.

15. The method of claim 11 further comprising bonding a second die to a first die in the wafer.

16. The method of claim 15, wherein the second die comprises:

a second semiconductor substrate;

a second interconnect structure comprising metal lines and vias in second dielectric layers and on a front side of the second semiconductor substrate; and

a second plurality of channels in the second dielectric layers, wherein after the step of bonding the second die to the first die, the first plurality of channels and the second plurality of channels are interconnected.

17. The method of claim 11 further comprising attaching a first fluidic tube to a first opening left by a first one of the removed TSVs and a second opening left by a second one of the removed TSVs.

18. A method comprising:

forming a through-substrate via (TSV) extending into a semiconductor substrate;

forming an interconnect structure comprising dielectric layers and metal features in the dielectric layers, wherein the interconnect structure is on a front side of the semiconductor substrate, and the metal features form interconnected metal pipes encircling a region of the interconnect structure;

etching portions of the dielectric layers in the region to form a first channel in the dielectric layers;

sealing the first channel with a film, wherein the film and the TSV are on opposite sides of the interconnect structure;

polishing a backside of the semiconductor substrate to expose the TSV;

etching the TSV to form a second channel in the semiconductor substrate; and

etching a metal feature exposed to the second channel to interconnect the first channel and the second channel as a continuous channel.

19. The method of claim 18 further comprising attaching a fluidic tube to the second channel.

20. The method of claim 18, wherein the semiconductor substrate is comprised in a first die, and the method further comprises bonding a second die to the first die.