Method for making a dielectric region in a bulk silicon substrate providing a high-Q passive resonator

• US 9,355,972 B2
• Filed: 03/04/2014
• Issued: 05/31/2016
• Est. Priority Date: 03/04/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dunn, James S., He, Zhong-Xiang, Liu, Qizhi
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): LIU, MIKKA H
• Application Number:
  US14/196,137
• Publication Number:
  US 20150255528A1
• Time in Patent Office: 819 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Claims

1. A method of making a dielectric region to provide a high-Q passive resonator in a mixed-signal integrated circuit (IC), said method comprising:

patterning and etching a hard mask to form a plurality of holes along <

100>

directions that overlie a bulk Si substrate of a (100) Si wafer;

etching said bulk Si substrate through said plurality of holes, said etching forming a plurality of trenches with vertical sidewalls;

wet etching said plurality of trenches, said wet etching providing a plurality of cavities with thin Si sidewalls between adjacent cavities and said wet etching removing undercut regions in said cavities;

oxidizing the sidewalls of said plurality of cavities, including said thin Si sidewalls, said oxidizing forming Si oxide sidewalls in said cavities;

filling said plurality of cavities with a Si oxide forming said dielectric region including a plurality of Si oxide filled cavities separated by said Si oxide sidewalls;

depositing and planarizing a dielectric layer over said hard mask and said dielectric region; and

forming said high-Q passive resonator in metallization layers associated with back-end-of-line (BEOL) processes in making of said mixed-signal IC, said metallization layers being over said dielectric region.

2. The method of claim 1, further comprising depositing a topmost front-end-of-line (FEOL) layer, associated with FEOL processes in said making of said mixed-signal IC, on said dielectric layer before said forming of said high-Q passive resonator.

3. The method of claim 1, said hard mask comprising one of a silicon oxide and a silicon nitride.

4. The method of claim 1, said plurality of holes including any of square holes, rectangular holes, and a combination of square holes and rectangular holes.

5. The method of claim 1, said etching comprising a reactive ion etching process, which provides said vertical sidewalls of an anisotropic etch profile.

6. The method of claim 1, said wet etching being accomplished by anisotropic wet etchants, including any of ethylenediamine pyrocatechol (EDP), potassium hydroxide/isopropyl alcohol (KOH/IPA), and tetramethylammonium hydroxide (TMAH), ammonia hydroxide, and ammonia hydroxide.

7. The method of claim 1, said oxidizing said sidewalls comprising using high pressure wet oxidation (HiPOX) at a low temperature ranging from 500°

to 800°

C.

8. The method of claim 1, said dielectric layer comprising one of a silicon oxide and a silicon nitride.

9. The method of claim 1, said high-Q passive resonator comprising one of an inductor and a capacitor.

10. A method of making a dielectric region to provide a high-Q passive resonator in a mixed-signal integrated circuit (IC), said method comprising:

patterning and etching a hard mask to form a plurality of holes along <

100>

directions that overlie a bulk Si substrate of a (100) Si wafer;

etching said bulk Si substrate through said plurality of holes, to form a plurality of trenches;

wet etching said plurality of trenches, to provide a plurality of cavities;

oxidizing sidewalls of said plurality of cavities to form Si oxide sidewalls;

filling said plurality of cavities with a Si oxide to form said dielectric region; and

forming said high-Q passive resonator in metallization layers associated with back-end-of-line (BEOL) processes in making of said mixed-signal IC, said metallization layers being over said dielectric region.

11. The method of claim 10, further comprising depositing a topmost front-end-of-line (FEOL) layer, associated with FEOL processes in said making of said mixed-signal IC, before said forming of said high-Q passive resonator.

12. The method of claim 10, said etching comprising a reactive ion etching process, which provides vertical sidewalls of an anisotropic etch profile for said plurality of trenches.

13. The method of claim 10, said wet etching being accomplished by anisotropic wet etchants, including any of ethylenediamine pyrocatechol (EDP), potassium hydroxide/isopropyl alcohol (KOH/IPA), and tetramethylammonium hydroxide (TMAH), ammonia hydroxide, and ammonia hydroxide.

14. The method of claim 10, said oxidizing said sidewalls comprising using high pressure wet oxidation (HiPOX) at a low temperature.

15. A method comprising:

patterning a hardmask on a surface (100) of a bulk Si substrate of a Si wafer;

forming holes along <

100>

directions of said bulk Si substrate according to said hardmask;

forming trenches through said holes in said bulk Si substrate, said trenches comprising vertical sidewalls;

forming cavities in said trenches by wet etching said vertical sidewalls;

forming Si oxide sidewalls in said cavities by oxidizing remaining portions of said vertical sidewalls;

forming a dielectric region by filling said cavities with a Si oxide; and

forming a high-Q passive resonator over said dielectric region.

16. The method of claim 15, further comprising:

depositing a topmost front-end-of-line (FEOL) layer, associated with FEOL processes in making a mixed-signal IC, before said forming said high-Q passive resonator.

17. The method of claim 15, further comprising:

depositing a dielectric layer over said hard mask and said dielectric region; and

planarizing said dielectric layer.

18. The method of claim 15, said forming said trenches through said holes in said bulk Si substrate comprising using a reactive ion etching process, said reactive ion etching process providing an anisotropic etch profile for said trenches.

19. The method of claim 15, said wet etching being accomplished by anisotropic wet etchants, including any of ethylenediamine pyrocatechol (EDP), potassium hydroxide/isopropyl alcohol (KOH/IPA), and tetramethylammonium hydroxide (TMAH), ammonia hydroxide, and ammonia hydroxide.

20. The method of claim 15, said forming said Si oxide sidewalls in said cavities comprising using high pressure wet oxidation (HiPOX) at a low temperature ranging from 500°

to 800°

C.