Ring gate transistor design for flash memory

• US 9,356,105 B1
• Filed: 12/29/2014
• Issued: 05/31/2016
• Est. Priority Date: 12/29/2014
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Primary Examiner(s): Bernstein, Allison P
• Application Number:
  US14/584,871
• Time in Patent Office: 519 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory device includes a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal having the second conductivity type surrounding the channel region. A connector is in contact with the first terminal, and can be connected to a bit line in an overlying patterned conductor layer. Memory material is disposed over the channel region, and can include a dielectric charge storage structure. A control gate surrounds the first terminal and is disposed over the memory material. A conductive line surrounds the control gate and is in contact with the second terminal. The control gate and the conductive line can be ring shaped.

Claims

1. A memory device, comprising:

A ring gate cell, the ring gate cell comprising a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal in the semiconductor body having the second conductivity type surrounding the channel region;

a connector in contact with the first terminal;

memory material over the channel region;

a control gate surrounding the first terminal and over the memory material; and

a conductive line surrounding the control gate and in contact with the second terminal.

2. The device of claim 1, wherein the control gate and the conductive line are ring shaped.

3. The device of claim 1, the semiconductor body including a pickup terminal having the first conductivity type located outside the conductive line, and including a connector in contact with the pickup terminal.

4. The device of claim 1, wherein the connector in contact with the first terminal is connected to a bit line in an overlying patterned conductor layer.

5. The device of claim 1, wherein the conductive line is connected to a common source line in an overlying patterned conductor layer.

6. The device of claim 1, wherein the memory material comprises a dielectric charge storage structure.

7. The device of claim 1, including:

a second channel region in the semiconductor body surrounding the first mentioned channel region and inside the conductive line; and

a second gate surrounding the control gate and over the second channel region.

8. The device of claim 1, wherein the semiconductor body is planar between the first and second terminals.

9. The device of claim 1, wherein there are no insulator filled trenches in the semiconductor body between the first and second terminals.

10. The device of claim 1, including:

a plurality of concentric channel regions surrounding the first terminal, the plurality including said first mentioned channel region; and

a plurality of concentric gates over the plurality of concentric channel regions, the plurality of concentric gates including said control gate.

11. The memory device of claim 1, including an N-well, the semiconductor body inside the N-well, and the first terminal and the second terminal inside the semiconductor body and including N+ doping.

12. The memory device of claim 1, including an array of ring gate NOR cells, including said first mentioned ring gate cell, having respective first terminals, and including a first plurality of patterned conductor lines connected to the first terminals of the ring gate NOR cells in the array.

13. The memory device of claim 12, including a first plurality of conductors connecting respective control gates in a row of ring gate NOR cells in the array of ring gate NOR cells, wherein conductors in the first plurality of conductors are coupled to word line decoding circuitry.

14. The memory device of claim 13, further comprising:

a second gate surrounding the control gate and between the control gate and the conductive line; and

a gate dielectric layer between the second gate and the semiconductor body, including a second plurality of conductors connecting respective second gates in the row,

wherein conductors in the second plurality of conductors are coupled to the word line decoding circuitry; and

wherein the gate dielectric layer includes material different than the memory material.

15. The memory device of claim 12, including a conductor connecting the conductive lines surrounding respective control gates in ring gate NOR cells in the array.

16. The memory device of claim 12, wherein the array of ring gate NOR cells is disposed in a first region on a substrate, and the memory device including a multilayer array of NOR cells disposed in a second region on the substrate, wherein:

the multilayer array of NOR cells is disposed in a plurality of levels on the substrate;

the array of ring gate NOR cells is disposed on an upper level in the plurality of levels; and

NOR cells in the multilayer array of NOR cells are disposed in at least some levels lower than the upper level.

17. A memory device, comprising:

a ring gate NAND cell, the ring gate NAND cell comprising a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, and a second terminal in the semiconductor body having the second conductivity type;

a connector in contact with the first terminal;

a plurality of concentric gates surrounding the first terminal and over the semiconductor body, including at least an inner concentric gate surrounding the first terminal, a plurality of intermediate concentric gates surrounding the inner concentric gate, and an outer concentric gate surrounding the plurality of intermediate concentric gates;

memory material between the plurality of intermediate concentric gates and the semiconductor body, and a gate dielectric layer between the inner concentric gate and the semiconductor body and between the outer concentric gate ring and the semiconductor body; and

a conductive line surrounding the plurality of concentric gates and in contact with the second terminal.

18. The memory device of claim 17, including an N-well, the semiconductor body inside the N-well, and the first terminal and the second terminal inside the semiconductor body and including N+ doping.

19. The memory device of claim 17, wherein the gate dielectric layer includes the memory material.

20. The memory device of claim 17, including an array of ring gate NAND cells, including said first mentioned ring gate NAND cell, having respective first terminals, and including a first plurality of patterned conductor lines (361, 362) connected to the first terminals of the ring gate NAND cells in the array.

21. The memory device of claim 20, wherein:

patterned conductor lines in the first plurality of patterned conductor lines have a first pitch;

ring gate NAND cells in the array have a ring gate NAND cell pitch greater than the first pitch; and

a row of ring gate NAND cells in the array of ring gate NAND cells is placed with an offset to match the first pitch.

22. The memory device of claim 20, including:

a plurality of conductors connecting respective concentric gates in the plurality of concentric gates in a row of ring gate NAND cells in the array of ring gate NAND cells, wherein;

conductors in the plurality of conductors connected to inner concentric gates in the plurality of concentric gates are coupled to first decoding circuitry;

conductors in the plurality of conductors connected to intermediate concentric gates in the plurality of concentric gates are coupled to second decoding circuitry; and

conductors in the plurality of conductors connected to outer concentric gates in the plurality of concentric gates are coupled to third decoding circuitry.

23. The memory device of claim 20, wherein the conductive lines surrounding the respective pluralities of concentric gates in ring gate NAND cells in the array are connected by a conductor.

24. The memory device of claim 20, wherein the array of ring gate NAND cells is disposed in a first region on a substrate, and including a multilayer array of NAND strings disposed in a second region on the substrate.

25. The memory device of claim 24, wherein the multilayer array comprises:

active strips disposed in a plurality of levels on the substrate;

a plurality of structures of a conductive material arranged orthogonally over the active strips in the plurality of levels; and

memory elements in interface regions at cross-points between surfaces of the active strips in the plurality of levels and the plurality of structures.

26. The memory device of claim 25, wherein the array of ring gate NAND cells is disposed on an upper level in the plurality of levels, and the active strips are disposed in at least some levels lower than the upper level, further comprising:

interlayer connectors connected to the active strips disposed in the plurality of levels, the interlayer connectors extending from respective levels in the plurality of levels to a connector surface higher than a top level in the plurality of levels; and

a second plurality of patterned conductor lines on top of the connector surface and connected to the respective interlayer connectors, wherein

patterned conductor lines in the first plurality of patterned conductor lines have a first pitch; and

patterned conductor lines in the second plurality of patterned conductor lines have a second pitch that matches the first pitch.