Metal gate transistor and method for tuning metal gate profile

• US 9,356,120 B2
• Filed: 12/31/2013
• Issued: 05/31/2016
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Po-Chi, Fang, Buh-Kuan, Chang, Yung-Jung, Leu, Po-Hsiung
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US14/145,684
• Publication Number:
  US 20150187939A1
• Time in Patent Office: 882 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer;

depositing a tensile ILD layer between the plurality of dummy gate structures;

removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches;

after removing the at least the dummy gate material, stressing the tensile ILD layer by at least one of annealing, chemically treating, and exposing to UV radiation; and

after stressing the tensile ILD layer, depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile.

2. The method of claim 1, wherein the depositing a tensile ILD layer exposes an area between the plurality of dummy gate structures to a siloxane precursor in a high aspect ratio process (HARP).

3. The method of claim 2, wherein the depositing a tensile ILD layer also includes exposing the siloxane precursor to a remote plasma.

4. The method of claim 2, wherein the siloxane precursor is an alkoxysilane precursor.

5. The method of claim 1, wherein the at least the dummy gate material includes material of the first gate dielectric layer and the method further comprises depositing a second gate dielectric.

6. The method of claim 5, wherein the second gate dielectric comprises HfO₂, TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, or ZrSiO₂.

7. The method of claim 1, wherein the first gate dielectric layer is a high k dielectric layer having a dielectric constant, k, greater than or equal to about 4.0.

8. The method of claim 1, wherein the depositing a metal gate material comprises depositing a work function metal and a fill metal.

9. The method of claim 1, wherein the tensile ILD layer has a tensile stress of about 200 MPa to about 1400 MPa after the stressing.

10. The method of claim 1, wherein the dummy gate material layer is polysilicon.

11. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer;

depositing a tensile ILD layer between the plurality of dummy gate structures;

stressing the tensile ILD layer with at least one of an annealing process, a chemical treatment process, and a UV radiation exposure process;

after stressing the tensile ILD layer, removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; and

depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile.

12. The method of claim 11, wherein the depositing a tensile ILD layer includes exposing an area between the plurality of dummy gate structures to a siloxane precursor in a high aspect ratio process (HARP) and exposing the siloxane precursor to a remote plasma.

13. The method of claim 12, wherein the siloxane precursor is an alkoxysilane precursor.

14. The method of claim 11, wherein the at least the dummy gate material includes material of the first gate dielectric layer and the method further comprises depositing a second gate dielectric.

15. The method of claim 14, wherein the at least the dummy gate material comprises polysilicon.

16. The method of claim 11, wherein the depositing a metal gate material comprises depositing a work function metal and a fill metal.

17. The method of claim 11, wherein the tensile ILD layer has a tensile stress of about 200 MPa to about 1400 MPa after the stressing.

18. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer;

depositing a tensile ILD layer between the plurality of dummy gate structures;

annealing the tensile ILD layer;

after annealing the tensile ILD layer, removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; and

depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile.

19. The method of claim 18, wherein the tapered profile has a width difference between a width of an upper portion of the tapered profile and a width of a lower portion of the tapered profile of up to about 3 nm.

20. The method of claim 19, wherein the width of the upper portion of the tapered profile is larger than the width of the lower portion of the tapered profile.