Metal gate transistor and method for tuning metal gate profile
First Claim
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1. A method of fabricating a semiconductor device, the method comprising:
- forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer;
depositing a tensile ILD layer between the plurality of dummy gate structures;
removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches;
after removing the at least the dummy gate material, stressing the tensile ILD layer by at least one of annealing, chemically treating, and exposing to UV radiation; and
after stressing the tensile ILD layer, depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile.
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Abstract
A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.
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Citations
20 Claims
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1. A method of fabricating a semiconductor device, the method comprising:
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forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer; depositing a tensile ILD layer between the plurality of dummy gate structures; removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; after removing the at least the dummy gate material, stressing the tensile ILD layer by at least one of annealing, chemically treating, and exposing to UV radiation; and after stressing the tensile ILD layer, depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a semiconductor device, the method comprising:
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forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer; depositing a tensile ILD layer between the plurality of dummy gate structures; stressing the tensile ILD layer with at least one of an annealing process, a chemical treatment process, and a UV radiation exposure process;
after stressing the tensile ILD layer, removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; anddepositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method of fabricating a semiconductor device, the method comprising:
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forming a plurality of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer; depositing a tensile ILD layer between the plurality of dummy gate structures; annealing the tensile ILD layer; after annealing the tensile ILD layer, removing at least the dummy gate material from the plurality of dummy gate structures to form a plurality of trenches; and depositing a metal gate material in the plurality of trenches, wherein each of the plurality of trenches has a tapered profile. - View Dependent Claims (19, 20)
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Specification