Integrating Schottky diode into power MOSFET

• US 9,356,132 B2
• Filed: 06/27/2014
• Issued: 05/31/2016
• Est. Priority Date: 05/02/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Su, Yi, Ng, Daniel, Bhalla, Anup, Chang, Hong, Kim, Jongoh, Chen, John
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US14/318,408
• Publication Number:
  US 20160005853A1
• Time in Patent Office: 704 Days
• Field of Search: 438/178, 438/237, 438/270, 438/268, 257/284, 257327-334
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Claims

1. A semiconductor device, comprising:

a) a first and second trenches on a substrate that define a mesa of a first conductivity type having a first width between the first and second trenches;

b) an insulated source electrode formed in the first and second trenches;

c) a dielectric region formed in at least a portion of the first and second trenches insulating the insulated source electrode from the mesa, wherein a portion of the dielectric region fills a top portion of the first and second trenches;

d) a dielectric layer formed on a top surface of the mesa having a contact opening through the dielectric layer; and

e) a surface source electrode electrically connected to the insulated source electrode overlaying the dielectric layer and filling the contact opening forming a Schottky junction at an interface with the mesa.

2. The semiconductor device of claim 1, wherein the contact opening further comprises a contact trench extending to a first depth into the mesa.

3. The semiconductor device of claim 1, wherein the contact opening has a width less than the first width.

4. The semiconductor device of claim 1, further comprising an insulated gate electrode formed in the first and second trenches overlying the insulated source electrode, wherein the insulated gate electrode is electrically isolated from the insulated source electrode by a portion of the dielectric region.

5. The semiconductor device of claim 1, further comprising a floating doped region of a second conductivity type formed in the first conductivity mesa aligned to the contact opening.

6. The semiconductor device of claim 5, wherein the second conductivity type is opposite to the first conductivity type.

7. The semiconductor device of claim 5, wherein the floating doped region of the second conductivity type has a width substantially the same as the width of the contact opening.

8. The semiconductor device of claim 5, wherein the contact opening further comprises a contact trench extending to a first depth into the mesa and the floating doped region of the second conductivity type is formed in the mesa at a second depth deeper than the first depth.

9. A semiconductor device, comprising:

a) a first and second trenches on a substrate that define a mesa of a first conductivity type having a first width between the first and second trenches;

b) an insulated shielding electrode formed in the first and second trenches;

c) a dielectric region formed in at least a portion of the first and second trenches insulating the insulated shielding electrode from the mesa, wherein a portion of the dielectric region filling a top portion of the first and second trenches;

d) a dielectric layer formed on a top surface of the mesa having a contact opening through the dielectric layer, wherein the contact opening further comprising a contact trench extending to a first depth into the mesa having an entire sidewall and a bottom surrounded by the mesa of the first conductivity type; and

e) a surface electrode overlaying the dielectric layer and filling the contact trench forming a Schottky junction at an interface with the mesa.

10. The semiconductor device of claim 9, further comprising an insulated gate electrode formed in the first and second trenches overlying the insulated source electrode, wherein the insulated gate electrode is electrically isolated from the insulated source electrode by a portion of the dielectric region.

11. The semiconductor device of claim 9, wherein the insulated shielding electrode being electrically connected to the surface electrode.

12. The semiconductor device of claim 9, further comprising a floating doped region of second conductivity type formed in the first conductivity mesa aligned to the contact trench.

13. The semiconductor device of claim 12, wherein the second conductivity type is opposite to the first conductivity type.

14. The semiconductor device of claim 12, wherein the floating doped region of second conductivity type having a width substantially the same as the contact trench.