Power MOS device structure

• US 9,356,137 B2
• Filed: 05/07/2013
• Issued: 05/31/2016
• Est. Priority Date: 05/10/2012
• Status: Active Grant

• Current Assignee: CSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
• Original Assignee: CSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
• Inventors: Zhang, Shu, He, Yanqiang, Lo, TseHuang, Wu, HsiaoChia
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US14/130,483
• Publication Number:
  US 20140159151A1
• Time in Patent Office: 1,120 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/07 Structure, shape, material or disposition of the bonding areas after the connecting process
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Claims

1. A power MOS device structure, comprising:

a semiconductor substrate having a plurality of basic units of lateral double-diffused metal-oxide semiconductor (LDMOS) formed thereon;

a first metal layer disposed above the semiconductor substrate;

a second metal layer disposed above the first metal layer and having a plurality of bonding pads; and

a plurality of metal plugs disposed between and electrically connecting the first metal layer and the second metal layer,

wherein;

the basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple a gate terminal, a source terminal, a drain terminal and a substrate terminal of each of the basic units of LDMOS to the bonding pads,

at least one of the basic units of LDMOS is disposed directly below a respective bonding pad of the plurality of bonding pads, and

each of the gate terminal, the source terminal, the drain terminal and the substrate terminal of the at least one of the basic units of LDMOS disposed directly below the respective bonding pad is firstly coupled to a region outside a perimeter of the respective bonding pad via the first metal layer, and then subsequently coupled to at least one of the bonding pads via at least one of the plurality of metal plugs and the second metal layer.

2. The power MOS device structure of claim 1, further comprising a first metal layer disposed between the plurality of basic units of LDMOS and the plurality of bonding pads, wherein the basic units of LDMOS, the first metal layer and the bonding pads are electrically coupled by metal plugs.

3. The power MOS device structure of claim 1, wherein the plurality of bonding pads comprises a gate bonding pad, a source bonding pad, a drain bonding pad, and a substrate bonding pad that are coupled to the gate terminal, source terminal, drain terminal, and source terminal of each of the plurality of basic units of LDMOS which are coupled in parallel.

4. The power MOS device structure of claim 1, wherein the plurality of bonding pads comprises a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um, the single layer of metal comprising aluminum-copper metal or aluminum-silicon-copper metal.

5. The power MOS device structure of claim 4, wherein the plurality of bonding pads further comprises a barrier layer below the single layer of metal.

6. The power MOS device structure of claim 5, wherein the barrier layer comprises a titanium layer and a titanium nitride layer, a thickness of the titanium layer being 300 Å

˜

600 Å and

a thickness of the titanium nitride layer being 300 Å

˜

800 Å

.

7. The power MOS device structure of claim 4, wherein the plurality of bonding pads further comprise an anti-reflection layer above the single layer of metal.

8. The power MOS device structure of claim 7, wherein the anti-reflection layer comprises a titanium layer and a titanium nitride layer, a thickness of the titanium layer being 100 Å

-400 Å and

a thickness of the titanium nitride layer being 250 Å

˜

400 Å

.

9. The power MOS device structure of claim 1, further comprising a passivation layer over a surface of the power MOS device structure with one or more openings exposing the plurality of bonding pads.

10. The power MOS device structure of claim 9, wherein the passivation layer comprises a layer of plasma-rich silicon oxide film having a thickness of 1 kÅ

to 2 kÅ

, a layer of high-density plasma silicon dioxide film having a thickness of 10 kÅ

to 20 kÅ and

disposed over the layer of plasma-rich silicon oxide film, and a layer of plasma silicon nitride film having a thickness of 7 kÅ

to 11 kÅ and

disposed over the layer of high-density plasma silicon dioxide film.