Power MOS device structure
First Claim
1. A power MOS device structure, comprising:
- a semiconductor substrate having a plurality of basic units of lateral double-diffused metal-oxide semiconductor (LDMOS) formed thereon;
a first metal layer disposed above the semiconductor substrate;
a second metal layer disposed above the first metal layer and having a plurality of bonding pads; and
a plurality of metal plugs disposed between and electrically connecting the first metal layer and the second metal layer,wherein;
the basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple a gate terminal, a source terminal, a drain terminal and a substrate terminal of each of the basic units of LDMOS to the bonding pads,at least one of the basic units of LDMOS is disposed directly below a respective bonding pad of the plurality of bonding pads, andeach of the gate terminal, the source terminal, the drain terminal and the substrate terminal of the at least one of the basic units of LDMOS disposed directly below the respective bonding pad is firstly coupled to a region outside a perimeter of the respective bonding pad via the first metal layer, and then subsequently coupled to at least one of the bonding pads via at least one of the plurality of metal plugs and the second metal layer.
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Accused Products
Abstract
Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.
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Citations
10 Claims
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1. A power MOS device structure, comprising:
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a semiconductor substrate having a plurality of basic units of lateral double-diffused metal-oxide semiconductor (LDMOS) formed thereon; a first metal layer disposed above the semiconductor substrate; a second metal layer disposed above the first metal layer and having a plurality of bonding pads; and a plurality of metal plugs disposed between and electrically connecting the first metal layer and the second metal layer, wherein; the basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple a gate terminal, a source terminal, a drain terminal and a substrate terminal of each of the basic units of LDMOS to the bonding pads, at least one of the basic units of LDMOS is disposed directly below a respective bonding pad of the plurality of bonding pads, and each of the gate terminal, the source terminal, the drain terminal and the substrate terminal of the at least one of the basic units of LDMOS disposed directly below the respective bonding pad is firstly coupled to a region outside a perimeter of the respective bonding pad via the first metal layer, and then subsequently coupled to at least one of the bonding pads via at least one of the plurality of metal plugs and the second metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification