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Power MOS device structure

  • US 9,356,137 B2
  • Filed: 05/07/2013
  • Issued: 05/31/2016
  • Est. Priority Date: 05/10/2012
  • Status: Active Grant
First Claim
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1. A power MOS device structure, comprising:

  • a semiconductor substrate having a plurality of basic units of lateral double-diffused metal-oxide semiconductor (LDMOS) formed thereon;

    a first metal layer disposed above the semiconductor substrate;

    a second metal layer disposed above the first metal layer and having a plurality of bonding pads; and

    a plurality of metal plugs disposed between and electrically connecting the first metal layer and the second metal layer,wherein;

    the basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple a gate terminal, a source terminal, a drain terminal and a substrate terminal of each of the basic units of LDMOS to the bonding pads,at least one of the basic units of LDMOS is disposed directly below a respective bonding pad of the plurality of bonding pads, andeach of the gate terminal, the source terminal, the drain terminal and the substrate terminal of the at least one of the basic units of LDMOS disposed directly below the respective bonding pad is firstly coupled to a region outside a perimeter of the respective bonding pad via the first metal layer, and then subsequently coupled to at least one of the bonding pads via at least one of the plurality of metal plugs and the second metal layer.

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