Pattern layout to prevent split gate flash memory cell failure

• US 9,356,142 B2
• Filed: 06/20/2014
• Issued: 05/31/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yu-Hsing, Wu, Chang-Ming, Liu, Shih-Chang
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US14/310,277
• Publication Number:
  US 20150372136A1
• Time in Patent Office: 711 Days
• Field of Search: 257/325, 438/275
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Claims

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a first source/drain region and a second source/drain region, wherein a channel region is arranged between the first and second source/drain regions;

a select gate and a memory gate spaced between the first and second source/drain regions over the channel region, wherein the select gate extends over the channel region and terminates at a line end having a top surface being asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate; and

a charge trapping dielectric structure arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate.

2. The semiconductor structure according to claim 1, wherein the select gate extends to the line end perpendicular to a length of the channel region, and wherein the width of the select gate extends parallel to the length of the channel region.

3. The semiconductor structure according to claim 1, wherein the line end is about 150-250 nanometers from the channel region.

4. The semiconductor structure according to claim 1, wherein a projection of the line end onto a top surface of the semiconductor substrate is one of circular, triangular, rectangular, square, and trapezoidal.

5. The semiconductor structure according to claim 1, wherein the width of the select gate is uniform while extending to the line end, and wherein the line end includes a width greater than the uniform width.

6. The semiconductor structure according to claim 1, wherein at least one of:

a width of the line end is about 70-160 nanometers; and

a length of the line end is about 50-150 nanometers.

7. The semiconductor structure according to claim 1, wherein the line end wraps around the memory gate and has a distal point that is even with or past a sidewall of the memory gate.

8. The semiconductor structure according to claim 1, wherein the semiconductor substrate further includes a third source/drain region, wherein the second source/drain region is arranged between the first and third source/drain regions, wherein the second and third source/drain regions form a second channel region therebewteen, and wherein the semiconductor structure further includes:

a second select gate and a second memory gate spaced between the second and third source/drain regions over the second channel region, wherein the second select gate extends over the second channel region and terminates at a second line end being asymmetric about a second axis that extends along a length of the second select gate and that bisects a width of the second select gate.

9. The semiconductor structure according to claim 8, wherein the line end and the second line end extend laterally away from the second source/drain region.

10. A semiconductor structure of a pair of split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including channel regions arranged in rows and columns between source and drain regions;

select gates individual to the rows and extending across and perpendicular to the channel regions of corresponding rows, wherein the select gates terminate at corresponding line ends having top surfaces asymmetric about corresponding axes that extend along lengths of the corresponding select gates and that bisect widths of the corresponding select gates;

memory gates corresponding to the select gates and spaced from the corresponding select gates between corresponding source and drain regions; and

charge trapping dielectric structures corresponding to the memory gates that are arranged between the corresponding memory gates and the select gates, and that are arranged under the corresponding memory gates.

11. The semiconductor structure of claim 10, wherein a projection of one of the line ends onto a top surface of the semiconductor substrate is one of circular, triangular, rectangular, square, and trapezoidal.

12. The semiconductor structure according to claim 10, wherein one of the select gates has a uniform width while extending to the corresponding line end, and wherein the corresponding line end includes a width greater than the uniform width.

13. The semiconductor structure according to claim 10, wherein one of the line ends wraps around a corresponding memory gate to a point that is even with or past a sidewall of the corresponding memory gate.

14. The semiconductor structure according to claim 10, wherein line ends of a pair of neighboring select gates extend laterally in opposite directions.

15. The semiconductor structure according to claim 14, wherein a first line end of the neighboring select gates is laterally offset from a second line end of the neighboring select gates in a direction that is normal to the opposite directions.

16. A semiconductor structure comprising:

a semiconductor substrate including a first source/drain region and a second source/drain region, wherein a channel region is arranged between the first and second source/drain regions; and

a select gate and a memory gate spaced between the first and second source/drain regions, wherein the select gate extends over the channel region and terminates at a line end having a top surface being asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate, and wherein the select gate extends to the line end perpendicular to a length of the channel region.

17. The semiconductor structure according to claim 16, further comprising:

a charge trapping dielectric structure arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate.

18. The semiconductor structure according to claim 16, wherein the width is substantially uniform while extending to the line end.

19. The semiconductor structure according to claim 16, wherein the line end extends laterally between opposing sidewalls, along a second axis that is orthogonal to the axis, and wherein one of the opposing sidewalls extends along a length of the select gate, and wherein another one of the opposing sidewalls is confined to the line end.

20. The semiconductor structure according to claim 16, wherein the line end extends laterally towards the memory gate, along a second axis that is orthogonal to the axis.