Remote gate protection diode for field effect transistors

• US 9,356,144 B1
• Filed: 08/11/2010
• Issued: 05/31/2016
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Mason, Philip, Kerr, Daniel Charles, Carroll, Michael
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): Tang, Sue
• Application Number:
  US12/854,563
• Time in Patent Office: 2,120 Days
• Field of Search: 257/328, 257/347, 257355-360, 257/363, 257/364
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors

Abstract

The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.

Claims

1. A semiconductor die comprising:

a plurality of field effect transistor (FET) elements, such that each of the plurality of FET elements has gate oxide, a gate connection node, which is electrically coupled to a first side of the gate oxide, and a first connection node, which is electrically coupled to a second side of the gate oxide opposite the first side through one of a source connection node or a drain connection node;

a gate oxide protection circuit coupled between a first gate oxide protection node and a second gate oxide protection node, the gate oxide protection circuit comprising at least one diode element;

a first plurality of resistive elements coupled between the gate connection node of each one of the plurality of FET elements and the first gate oxide protection node;

a second plurality of resistive elements coupled between the first connection node of each one of the plurality of FET elements and the second gate oxide protection node;

a first common resistive element coupled between the first gate oxide protection node and the first plurality of resistive elements; and

a second common resistive element coupled between the second gate oxide protection node and the second plurality of resistive elements,

wherein the gate oxide protection circuit is configured to protect the gate oxide of each of the plurality of FET elements by limiting a voltage between the gate connection node and the first connection node of each of the plurality of FET elements.

2. The semiconductor die of claim 1 wherein each of the plurality of FET elements is a body contacted FET element.

3. The semiconductor die of claim 2 wherein the plurality of FET elements are coupled in series to form a radio frequency (RF) switch.

4. The semiconductor die of claim 3 further comprising control circuitry configured to during an OFF state of the RF switch, provide a body bias signal to the each body of the plurality of FET elements, such that the each body and each corresponding source of the plurality of FET elements are reverse biased and the each body and each corresponding drain of the plurality of FET elements are reverse biased to provide reverse body biasing of each of the plurality of FET elements.

5. The semiconductor die of claim 4 wherein during the OFF state of the RF switch, a voltage at each gate of the plurality of FET elements is about equal to a voltage at a corresponding body of the plurality of FET elements.

6. The semiconductor die of claim 1 wherein the at least one diode element comprises a plurality of diode elements coupled in series.

7. The semiconductor die of claim 6 wherein an anode of one of the plurality of diode elements is coupled to the first gate oxide protection node and a cathode of another of the plurality of diode elements is coupled to the second gate oxide protection node.

8. The semiconductor die of claim 6 wherein an anode of one of the plurality of diode elements is coupled to the second gate oxide protection node and a cathode of another of the plurality of diode elements is coupled to the first gate oxide protection node.

9. The semiconductor die of claim 1 wherein an anode of the at least one diode element is coupled to the first gate oxide protection node and a cathode of the at least one diode element is coupled to the second gate oxide protection node.

10. The semiconductor die of claim 1 wherein an anode of the at least one diode element is coupled to the second gate oxide protection node and a cathode of the at least one diode element is coupled to the first gate oxide protection node.

11. The semiconductor die of claim 1 further comprising:

a substrate;

an insulating layer over the substrate; and

a semiconductor device layer over the insulating layer, such that the semiconductor device layer provides at least a portion of the plurality of FET elements.

12. The semiconductor die of claim 11 wherein the semiconductor die is a silicon-on-insulator (SOI) semiconductor die.

13. The semiconductor die of claim 12 wherein the semiconductor device layer is an SOI device layer.

14. The semiconductor die of claim 12 wherein the semiconductor device layer is a thin-film SOI device layer.

15. The semiconductor die of claim 11 wherein the semiconductor device layer is a thin-film device layer.