Logarithmic amplifier with universal demodulation capabilities

• US 9,356,561 B2
• Filed: 06/25/2015
• Issued: 05/31/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: DockOn AG
• Original Assignee: DockOn AG
• Inventors: Brown, Forrest, Rada, Patrick, Dupuy, Alexandre
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US14/750,406
• Publication Number:
  US 20150295543A1
• Time in Patent Office: 341 Days
• Field of Search: 329/347, 329/349, 329/352, 329/353, 329/369, 329/367, 327/350, 455/336, 331/37, 331/174
• US Class Current: 1/1
• CPC Class Codes: H01P 5/19 of the junction type
• CPC Class Codes: H01Q 21/0075 Stripline fed arrays H01Q21/065 takes precedence
• CPC Class Codes: H01Q 7/00 Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H03D 1/08 by means of non-linear two-pole elements H03D1/22, H03D1/26, H03D1/28 take precedence
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03D 11/04 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 11/08 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0098 by compensating temperature induced variations
• CPC Class Codes: H03D 7/02 by means of diodes H03D7/14 - H03D7/22 take precedence
• CPC Class Codes: H03D 7/12 by means of semiconductor devices having more than two electrodes H03D7/14 - H03D7/22 take precedence
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/166 using two or more quadrature frequency translation stages
• CPC Class Codes: H03F 1/08 Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03G 11/04 Limiting level dependent on strength of signal; Limiting level dependent on strength of carrier on which signal is modulated H03G11/008 takes precedence

Abstract

A logarithmic amplifier (LDA) is described that includes an amplifier configured to oscillate a modulated input signal, a feedback establishing a 180 degree phase shift between the amplifier input and the output and maintaining oscillation of the input signal, a parallel resonant circuit connected to the amplifier output causing the amplifier to resonate at or around a center frequency, and a controller connected to the amplifier input cyclically terminating oscillation of the input signal each time a pre-determined threshold of current is detected, the controller including a low pass filter configured to generate a second output signal having a repetition frequency. The LDA may be used for AM with or without a PLL and/or a superheterodyne. The LDA may be implemented as a mixer and used for phase demodulation. The LDA may be used for phase demodulation. The LDA may be used in place of a low noise amplifier.

Claims

1. A logarithmic amplifier configured as a low noise amplifier, comprising:

a local oscillator (LO) configured to generate first and second oscillation frequency signals;

a mixer coupled to the LO, configured to receive an input signal having a first frequency and including a modulated signal and electrical noise, receive the first oscillation frequency signal, and down convert the input signal to a first intermediate frequency;

an amplifier circuit configured to receive the down-converted input signal at an amplifier input coupled to the mixer, oscillate the down-converted input signal, and generate a first output signal at an amplifier output;

a feedback circuit coupled to the amplifier output and the amplifier input and configured to establish a 180 degree phase shift between the down-converted input signal and the first output signal, the feedback circuit including a single capacitor configured to maintain oscillation of the input signal;

a parallel resonant circuit connected to the amplifier output and configured to cause the amplifier circuit to resonate at or around a center frequency;

a controller circuit connected to the amplifier input and configured to cyclically terminate oscillation of the down-converted input signal each time a pre-determined threshold of voltage is detected, the controller circuit including a low pass filter configured to generate a second output signal having a repetition frequency and carrying amplitude and phase information of the input signal; and

a second mixer coupled to the LO, configured to receive the second oscillation frequency signal from the LO, and up convert the second output signal to substantially the first frequency.

2. The logarithmic amplifier of claim 1, further comprising:

a frequency to voltage converter coupled between the low pass filter and the second mixer, configured to convert the second output signal to a third intermediate frequency according to the repetition frequency, convert the second output signal to baseband, or both.

3. A logarithmic amplifier detector (LDA) mixer circuit, comprising:

an amplifier circuit configured to receive an input signal at an amplifier input, oscillate the input signal, and generate a first output signal at an amplifier output, wherein the input signal includes a modulated signal and electrical noise;

a feedback circuit coupled to the amplifier output and the amplifier input and configured to establish a 180 degree phase shift between the input signal and the first output signal, the feedback circuit comprising at least 2 capacitors configured to maintain oscillation of the input signal, the at least 2 capacitors coupled in series, wherein a middle point between the at least 2 capacitors is coupled to a local oscillator (LO) having an LO frequency, and wherein the middle point is substantially an electrical balance point;

a parallel resonant circuit connected to the amplifier output and configured to cause the amplifier circuit to resonate at or around a center frequency; and

a controller circuit connected to the amplifier input and configured to cyclically terminate oscillation of the input signal each time a pre-determined threshold of voltage is detected, the controller circuit including a low pass filter configured to generate a second output signal having a repetition frequency.

4. The LDA mixer circuit of claim 3, wherein the middle point is coupled to the LO through a matching network.

5. The LDA mixer circuit of claim 3, wherein the LO frequency is substantially equal to an input signal frequency, wherein the LO is configured to provide a low intermediate frequency conversion output, and wherein the second output contains the input signal modulation.

6. The LDA mixer circuit of claim 3, wherein the LO frequency is substantially equal to an input signal frequency, wherein the LO is configured to provide a zero intermediate frequency conversion output after coupling the second output to a frequency to voltage converter and low pass filter signal, and wherein the second output contains the input signal modulation.

7. The LDA mixer circuit of claim 3, wherein the LO frequency is not equal to an input signal frequency, wherein the LO is configured to provide a non-zero intermediate frequency conversion, and wherein the second output contains the input signal modulation shifted in frequency by a frequency difference between the input signal frequency and the LO frequency.

8. The LDA mixer circuit of claim 3, wherein the second output contains the input signal modulation, and wherein the input signal modulation comprises at least one of AM, FM, PM, PSK, QPSK, m-PSK, m-QAM, OOK, ASK, m-ASK, FSK, MSK, m-FSK, Gaussian filtered, filtered, OFDM, MIMO, DS-SS, or FH-SS modulation.

9. The LDA mixer circuit of claim 3, wherein the repetition frequency of the second output has a rate of change at least twice of an input signal information rate.

10. The LDA mixer circuit of claim 3, wherein the repetition frequency of the second output has at least twice the frequency of an input signal maximum symbol rate.

11. The LDA mixer circuit of claim 3, wherein the second output repetition frequency is at least twice the frequency bandwidth of an input signal modulation bandwidth.

12. The LDA mixer circuit of claim 3, wherein the second output repetition frequency is at least as large as the maximum of an input signal symbol rate frequency, or a frequency bandwidth of the input signal modulation, and wherein the mixer circuit is synchronized with the symbol rate.

13. The LDA mixer circuit of claim 3, wherein a signal generated by the LO is modulated by a modulation input signal, transmitted through the amplifier circuit, and output on the amplifier input.

14. The LDA mixer circuit of claim 3, wherein a transmit modulated signal applied to the LO and coupled to the amplifier circuit is transmitted to the amplifier input concurrently with a receive signal being received at the amplifier input and output from the controller circuit.

15. The LDA mixer circuit of claim 3, wherein a transmit modulated signal applied to the LO and coupled to the amplifier circuit is transmitted to the amplifier input prior to or after a receive signal is received at the amplifier input and output from the controller circuit.

16. The LDA mixer circuit of claim 3, wherein calibrating the electric balance point comprises:

adding a modulation signal to a signal generated by the LO coupled to the middle point, wherein a variation in the frequency rate of the second output is generated when there is an imbalance in the modulation; and

balancing the balance point by minimizing any variation of repetition frequency on the second output by varying at least one of the at least two capacitors.

17. The LDA mixer circuit of claim 16, wherein at least one of the at least two capacitors comprises at least one of a varicap, a binary capacitor system controlled by digital signal, a decimal capacitor system controlled by digital signal, or a capacitor system controlled by digital signal.

18. A quadrature demodulator comprising:

a first mixer circuit and a second mixer circuit, each comprising;

a logarithmic amplifier detector (LDA) circuit, including;

an amplifier circuit configured to receive an input signal at an amplifier input, oscillate the input signal, and generate a first output signal at an amplifier output, wherein the input signal includes a modulated signal and electrical noise;

a feedback circuit coupled to the amplifier output and the amplifier input and configured to establish a 180 degree phase shift between the input signal and the first output signal, the feedback circuit including at least 2 capacitors configured to maintain oscillation of the input signal, the at least 2 capacitors coupled in series, wherein a middle point between the at least 2 capacitors is coupled to a local oscillator (LO) having an LO frequency, and wherein the middle point is substantially an electrical balance point; and

a parallel resonant circuit connected to the amplifier output and configured to cause the amplifier circuit to resonate at or around a center frequency; and

a controller circuit connected to the amplifier input and configured to cyclically terminate oscillation of the input signal each time a pre-determined threshold of voltage is detected, the controller circuit including a low pass filter configured to generate a second output signal having a repetition frequency;

wherein a portion of the input signal is coupled to the amplifier input of each of the first and second mixers;

wherein the first and second mixers are coupled to a single LO with two outputs having a phase difference of 90 degrees; and

wherein the second output of the first mixer and the second output of the second mixer are processed to provide demodulated quadratic input signal information.

19. The quadrature demodulator claim of 18, wherein the input signal is separated into two portions using a power splitter.

20. The quadrature demodulator of claim 18, wherein the input signal is separated into two portions using an active circuit.

21. The quadrature demodulator of claim 18, wherein the two outputs of the LO having a phase difference of 90 degrees are generated by a 90-degree splitter.

22. The quadrature demodulator of claim 18, wherein a second LO frequency associated with the second mixer is divided by 2*N, N being a positive integer, having a phase difference of 90 degrees with a first LO frequency.

23. The quadrature demodulator of claim 18, wherein the second output of the first mixer and the second mixer circuits are each coupled to a frequency to voltage converter, a low pass filter, and an analog to digital converter (ADC), and wherein the quadratic demodulated information of the signal is provided by the ADC of each of the first and second mixer via phase and quadrature voltage outputs.

24. The quadrature demodulator of claim 18, wherein the second output of each of the first and second mixer circuit are coupled to a digital shaping, a N bit counter, a digital inversion, and a scaling function, and wherein the quadratic demodulated information of the signal is provided by the digital phase and quadrature voltage outputs.

25. The quadrature demodulator of claim 18, wherein the input signal is split into a first and a second input signal, with the second input signal being 90 degrees out of phase with the first input signal, the second input signal received by the second mixer circuit.