Broadband linear amplifier architecture by combining two distributed amplifiers

• US 9,356,564 B1
• Filed: 03/27/2014
• Issued: 05/31/2016
• Est. Priority Date: 03/27/2014
• Status: Active Grant

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Kang, Jongchan, Moon, Jeong-Sun
• Primary Examiner(s): Mottola, Steven J
• Assistant Examiner(s): Rahman, Hafizur
• Application Number:
  US14/228,169
• Time in Patent Office: 796 Days
• Field of Search: 330/253, 330295-296, 330/286
• US Class Current: 1/1
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/604 using FET's
• CPC Class Codes: H03F 3/607 using FET's

Abstract

A broadband linear amplifier including an input, a first distributed amplifier coupled to the input and having a bias for one of Class A or Class AB operation, the first distributed amplifier including a first plurality of field effect transistors and having a first output, a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier including a second plurality of field effect transistors and having a second output, and a summed output coupled to the first output and the second output, wherein gate widths of the first plurality of field effect transistors monotonically decrease from the input to the first output, and wherein gate widths of the second plurality of field effect transistors monotonically decrease from the input to the second output.

Claims

1. A broadband linear amplifier comprising:

an input;

a first distributed amplifier coupled to the input and having a bias for one of Class A or Class AB operation, the first distributed amplifier comprising a first plurality of field effect transistors (FETs), each FET of the first plurality of FETs having a gate, a drain and a source, and wherein the first distributed amplifier has a first output;

a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier comprising a second plurality of field effect transistors, each FET of the second plurality of FETs having a gate, a drain and a source, and wherein the second distributed amplifier has a second output;

a first plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the first plurality of serially connected variable delay lines or transmission line lengths is connected to a respective drain of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the first plurality of serially connected variable delay lines or transmission line lengths has a first serial delay line output;

a second plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the second plurality of serially connected variable delay lines or transmission line lengths is connected to a respective gate of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the second plurality of serially connected variable delay lines or transmission line lengths has a second serial delay line output;

a first passive feedback circuit coupled between the second serial delay line output and the first serial delay line output; and

a summed output coupled to the first output and the second output;

wherein for Class AB operation, the bias for the first distributed amplifier is set above a turn-on threshold voltage for the first distributed amplifier;

wherein for Class A operation, the bias for the first distributed amplifier is set higher than for class AB operation and relatively high compared to the turn-on threshold voltage for the first distributed amplifier; and

wherein for Class C operation, the bias for the second distributed amplifier is set below a turn-on threshold voltage for the second distributed amplifier;

wherein the first passive feedback circuit comprises a resistor connected in series to a capacitor.

2. The broadband linear amplifier of claim 1 wherein:

the bias for the first distributed amplifier is set to a negative gm3 point; and

the bias for the second distributed amplifier is set to a positive gm3 point;

wherein third harmonics of the first distributed amplifier are cancelled by harmonics of the second distributed amplifier.

3. The broadband linear amplifier of claim 1 further comprising:

a first input matching circuit coupled between the input and the first distributed amplifier;

a second input matching circuit coupled between the input and the second distributed amplifier;

a first output matching circuit coupled between the first output and the summed output; and

a second output matching circuit coupled between the second output and the summed output.

4. The broadband linear amplifier of claim 3 wherein:

the first input matching circuit comprises a pi network circuit;

the second input matching circuit comprises a pi network circuit;

the first output matching circuit comprises a pi network circuit; and

the second output matching circuit comprises a pi network circuit.

5. The broadband linear amplifier of claim 1 further comprising:

a Wilkinson power divider coupled to the input, the Wilkinson power divider coupled to the first distributed amplifier and the second distributed amplifier;

wherein the Wilkinson power divider divides power on the input between the first distributed amplifier and the second distributed amplifier.

6. The broadband linear amplifier of claim 1 wherein:

the bias for the first distributed amplifier comprises a first gate to source bias voltage coupled to the first plurality of field effect transistors; and

the bias for the second distributed amplifier comprises a second gate to source bias voltage coupled to the second plurality of field effect transistors.

7. The broadband linear amplifier of claim 6 further comprising:

a first drain to source bias voltage;

wherein each field effect transistor of the first plurality of field effect transistors has a drain coupled to the first drain to source bias voltage;

wherein each field effect transistor of the first plurality of field effect transistors has a source coupled to ground; and

wherein each field effect transistor of the first plurality of field effect transistors has a gate coupled to the first gate to source bias voltage; and

a second drain to source bias voltage;

wherein each field effect transistor of the second plurality of field effect transistors has a drain coupled to the second drain to source bias voltage;

wherein each field effect transistor of the second plurality of field effect transistors has a source coupled to ground; and

wherein each field effect transistor of the second plurality of field effect transistors has a gate coupled to the second gate to source bias voltage.

8. The broadband linear amplifier of claim 7 wherein:

the first plurality of serially connected variable delay lines or transmission line lengths is coupled to the first drain to source bias voltage for adjusting a delay between the first drain to source bias voltage and each drain of the first plurality of field effect transistors for tuning the first distributed amplifier; and

the second plurality of serially connected variable delay lines or transmission line lengths is coupled to the first gate to source bias voltage for adjusting a delay between the first gate to source bias voltage and each gate of the first plurality of field effect transistors for tuning the first distributed amplifier;

the third plurality of serially connected variable delay lines or transmission line lengths is coupled to the second drain to source bias voltage for adjusting a delay between the second drain to source bias voltage and each drain of the second plurality of field effect transistors for tuning the second distributed amplifier; and

the fourth plurality of serially connected variable delay lines or transmission line lengths is coupled to the second gate to source bias voltage for adjusting a delay between the second gate to source bias voltage and each gate of the second plurality of field effect transistors for tuning the second distributed amplifier.

9. The broadband linear amplifier of claim 8 further comprising:

a first inductor coupled between the first drain to source bias voltage and the first plurality of serially connected variable delay lines or transmission line lengths;

a second inductor coupled between the second drain to source bias voltage and the third plurality of serially connected variable delay lines or transmission line lengths;

a first choke resistor coupled between the first gate to source bias voltage and the second plurality of serially connected variable delay lines or transmission line lengths; and

a second choke resistor coupled between the second gate to source bias voltage and the fourth plurality of serially connected variable delay lines or transmission line lengths.

16. The broadband linear amplifier of claim 1:

wherein device sizes of the first plurality of field effect transistors monotonically decrease from the input to the first output; and

wherein device sizes of the second plurality of field effect transistors monotonically decrease from the input to the second output.

18. The broadband linear amplifier of claim 1 further comprising:

a third plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the third plurality of serially connected variable delay lines or transmission line lengths is connected to a respective drain of a respective FET of the second plurality of field effect transistors for tuning the second distributed amplifier, and wherein the third plurality of serially connected variable delay lines or transmission line lengths has a third serial delay line output;

a fourth plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the fourth plurality of serially connected variable delay lines or transmission line lengths is connected to a respective gate of a respective FET of the second plurality of field effect transistors for tuning the second distributed amplifier, and wherein the fourth plurality of serially connected variable delay lines or transmission line lengths has a fourth serial delay line output; and

a second passive feedback circuit coupled between the fourth serial delay line output and the third serial delay line output.

20. The broadband linear amplifier of claim 18 wherein the second passive feedback circuit comprises a resistor connected in series to a capacitor.

10. A method of providing a broadband linear amplifier comprising:

providing a first distributed amplifier coupled to an input and having a bias for one of Class A or Class AB operation, the first distributed amplifier comprising a first plurality of field effect transistors (FETs), each FET of the first plurality of FETs having a gate, a drain and a source, and wherein the first distributed amplifier has a first output;

providing a second distributed amplifier coupled to the input and having a bias for Class C operation, the second distributed amplifier comprising a second plurality of field effect transistors, each FET of the second plurality of FETs having a gate, a drain and a source, and wherein the second distributed amplifier has a second output;

providing a first plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the first plurality of serially connected variable delay lines or transmission line lengths is connected to a respective drain of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the first plurality of serially connected variable delay lines or transmission line lengths has a first serial delay line output;

providing a second plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the second plurality of serially connected variable delay lines or transmission line lengths is connected to a respective gate of a respective FET of the first plurality of field effect transistors for tuning the first distributed amplifier, and wherein the second plurality of serially connected variable delay lines or transmission line lengths has a second serial delay line output;

providing a first passive feedback circuit coupled between the second serial delay line output and the first serial delay line output; and

forming a summed output of the first output and the second output;

wherein for Class AB operation, the bias for the first distributed amplifier is set above a turn-on threshold voltage for the first distributed amplifier;

wherein for Class A operation, the bias for the first distributed amplifier is set higher than for class AB operation and relatively high compared to the turn-on threshold voltage for the first distributed amplifier; and

wherein for Class C operation, the bias for the second distributed amplifier is set below a turn-on threshold voltage for the second distributed amplifier;

wherein the first passive feedback circuit comprises a resistor connected in series to a capacitor.

11. The method of claim 10 wherein:

the bias for the first distributed amplifier is set to a negative gm3 point; and

the bias for the second distributed amplifier is set to a positive gm3 point;

wherein third harmonics of the first distributed amplifier are cancelled by harmonics of the second distributed amplifier.

12. The method of claim 10 further comprising:

providing a first input matching circuit coupled between the input and the first distributed amplifier;

providing a second input matching circuit coupled between the input and the second distributed amplifier;

providing a first output matching circuit coupled between the first output and the summed output; and

providing a second output matching circuit coupled between the second output and the summed output;

wherein;

the first input matching circuit comprises a pi network circuit;

the second input matching circuit comprises a pi network circuit;

the first output matching circuit comprises a pi network circuit; and

the second output matching circuit comprises a pi network circuit.

13. The method of claim 10 wherein:

the bias for the first distributed amplifier comprises a first gate to source bias voltage coupled to the first plurality of field effect transistors; and

the bias for the second distributed amplifier comprises a second gate to source bias voltage coupled to the second plurality of field effect transistors.

14. The method of claim 13 further comprising:

providing a first drain to source bias voltage;

wherein each field effect transistor of the first plurality of field effect transistors has a drain coupled to the first drain to source bias voltage;

wherein each field effect transistor of the first plurality of field effect transistors has a source coupled to ground; and

wherein each field effect transistor of the first plurality of field effect transistors has a gate coupled to the first gate to source bias voltage; and

providing a second drain to source bias voltage;

wherein each field effect transistor of the second plurality of field effect transistors has a drain coupled to the second drain to source bias voltage;

wherein each field effect transistor of the second plurality of field effect transistors has a source coupled to ground; and

wherein each field effect transistor of the second plurality of field effect transistors has a gate coupled to the second gate to source bias voltage.

15. The method of claim 14 wherein:

the first plurality of serially connected variable delay lines or transmission line lengths is coupled to the first drain to source bias voltage for adjusting a delay between the first drain to source bias voltage and each drain of the first plurality of field effect transistors for tuning the first distributed amplifier;

the second plurality of serially connected variable delay lines or transmission line lengths is coupled to the first gate to source bias voltage for adjusting a delay between the first gate to source bias voltage and each gate of the first plurality of field effect transistors for tuning the first distributed amplifier;

the third plurality of serially connected variable delay lines or transmission line lengths is coupled to the second drain to source bias voltage for adjusting a delay between the second drain to source bias voltage and each drain of the second plurality of field effect transistors for tuning the second distributed amplifier; and

the fourth plurality of serially connected variable delay lines or transmission line lengths is coupled to the second gate to source bias voltage for adjusting a delay between the second gate to source bias voltage and each gate of the second plurality of field effect transistors for tuning the second distributed amplifier.

17. The method of claim 10:

wherein device sizes of the first plurality of field effect transistors monotonically decrease from the input to the first output; and

wherein device sizes of the second plurality of field effect transistors monotonically decrease from the input to the second output.

19. The method of claim 10 further comprising:

providing a third plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the third plurality of serially connected variable delay lines or transmission line lengths is connected to a respective drain of a respective FET of the second plurality of field effect transistors for tuning the second distributed amplifier, and wherein the third plurality of serially connected variable delay lines or transmission line lengths has a third serial delay line output;

providing a fourth plurality of serially connected variable delay lines or transmission line lengths, wherein each respective variable delay line or transmission line length of the fourth plurality of serially connected variable delay lines or transmission line lengths is connected to a respective gate of a respective FET of the second plurality of field effect transistors for tuning the second distributed amplifier, and wherein the fourth plurality of serially connected variable delay lines or transmission line lengths has a fourth serial delay line output; and

providing a second passive feedback circuit coupled between the fourth serial delay line output and the third serial delay line output.

21. The method of claim 19 wherein the second passive feedback circuit comprises a resistor connected in series to a capacitor.