Method and apparatus for evaluating and optimizing a signaling system

• US 9,356,743 B2
• Filed: 06/27/2014
• Issued: 05/31/2016
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): Hossain, Sazzad
• Application Number:
  US14/318,557
• Publication Number:
  US 20150078426A1
• Time in Patent Office: 704 Days
• Field of Search: 370/242, 370/249, 370/252, 375/221, 375/224, 714/715, 714/745, 714/708, 714/738, 714/712, 714/716, 714/735, 714/739
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/242 : by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/243 : at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 : test sequence generators
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 5/1438 : Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. An integrated circuit, comprising:

a receiver to serially receive a signal via at least one electrical conductor from a transmitter and to equalize the signal using a set of equalization coefficients, the signal comprising a repeating test pattern during a test mode and a data signal during a normal mode; and

circuitry to evaluate the repeating test pattern received by the receiver during the test mode against an expected pattern to generate comparison outputs using first values of the set of equalization coefficients during a first time period and second values of the set of equalization coefficients during a second time period;

where the receiver is to equalize the data signal during the normal mode using the first or the second values for the set of equalization coefficients selected in dependence on the comparison outputs.

2. The integrated circuit of claim 1, where the integrated circuit comprises a shift register to store values and to generate elements of the expected pattern during the test mode as a repeating pattern signal, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

3. The integrated circuit of claim 2, where the shift register is a linear feedback shift register.

4. The integrated circuit of claim 3, where the shift elements are to successively convey data values to be carried by the data signal during the normal mode and, further, where the repeating pattern signal to be generated during the test mode is to be seeded by data values carried by the data signal during the normal mode.

5. The integrated circuit of claim 1, where the transmitter is external to the integrated circuit, where the at least one electrical conductor comprises a differential path conductor, and where the receiver is embodied as a differential receiver that is to serially receive the data signal as a differential signal.

6. The integrated circuit of claim 1, where the receiver comprises two circuits to respectively latch even and odd data values serially carried by the data signal during the normal mode, and where the two circuits are to be periodically actuated to latch the even and odd data values as parallel output data.

7. The integrated circuit of claim 1, where the receiver comprises a series of storage elements to store a set of data values received from the data signal during the normal mode, and where the series of storage elements are to be periodically actuated as a group to latch the set of values as parallel output data.

8. The integrated circuit of claim 7, where the series of storage elements are embodied as a shift register to store values and to generate elements of the expected pattern during the test mode as a repeating pattern signal, and where the repeating pattern signal has a data length greater than a number of storage elements of the shift register.

9. An integrated circuit, comprising:

a receiver to serially receive a signal via at least one electrical conductor from a transmitter and to equalize the signal using at least one equalization coefficient, the signal comprising a repeating test pattern during a test mode and a data signal during a normal mode; and

circuitry to evaluate the repeating test pattern received by the receiver during the test mode against an expected pattern to generate comparison outputs while using different values for the at least one equalization coefficient;

wherein the receiver is to equalize the data signal during the normal mode using one of the different values for the at least one equalization coefficient selected in dependence on the comparison outputs.

10. The integrated circuit of claim 9, where the integrated circuit comprises a shift register to store values and to generate elements of the expected pattern during the test mode as a repeating pattern signal, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

11. The integrated circuit of claim 10, where the shift register is a linear feedback shift register.

12. The integrated circuit of claim 11, where the shift elements are to successively convey data values to be carried by the data signal during the normal mode and, further, where the repeating pattern signal to be generated during the test mode is to be seeded by data values carried by the data signal during the normal mode.

13. The integrated circuit of claim 9, where the transmitter is external to the integrated circuit, where the at least one electrical conductor comprises a differential path conductor, and where the receiver is embodied as a differential receiver that is to serially receive the data signal as a differential signal.

14. The integrated circuit of claim 9, where the receiver comprises two circuits to respectively latch even and odd data values serially carried by the data signal during the normal mode, and where the two circuits are to be periodically actuated to latch the even and odd data values as parallel output data.

15. The integrated circuit of claim 9, where the receiver comprises a series of storage elements to store a set of data values received from the data signal during the normal mode, and where the series of storage elements are to be periodically actuated as a group to latch the set of values as parallel output data.

16. The integrated circuit of claim 15, where the series of storage elements are embodied as a shift register to store values and to generate elements of the expected pattern during the test mode as a repeating pattern signal, and where the repeating pattern signal has a data length greater than a number of storage elements of the shift register.

17. An integrated circuit, comprising:

a receiver to serially receive a signal via at least one electrical conductor from a transmitter and to equalize the signal using a set of equalization coefficients, the signal comprising a repeating test pattern during a test mode and a data signal during a normal mode; and

circuitry to evaluate the repeating test pattern received by the receiver during the test mode against an expected pattern to generate comparison outputs while using different values for at least equalization coefficient of the equalization coefficients in the set;

wherein the receiver is to equalize the data signal during the normal mode using the set of equalization coefficients including one of the different values selected in dependence on the comparison outputs.

18. The integrated circuit of claim 17, where the transmitter is external to the integrated circuit, where the at least one electrical conductor comprises a differential path conductor, and where the receiver is embodied as a differential receiver that is to serially receive the data signal as a differential signal.

19. The integrated circuit of claim 17, where the receiver comprises two circuits to respectively latch even and odd data values serially carried by the data signal during the normal mode, and where the two circuits are to be periodically actuated to latch the even and odd data values as parallel output data.

20. The integrated circuit of claim 17, where the receiver comprises a series of storage elements to store a set of data values received from the data signal during the normal mode, and where the series of storage elements are to be periodically actuated as a group to latch the set of values as parallel output data.