Phase detecting circuit for interchain local oscillator (LO) divider phase alignment

• US 9,356,768 B2
• Filed: 09/24/2014
• Issued: 05/31/2016
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, David Ta-Hsiang, Ding, Yongwang, Kim, Young Gon, Nguyen, Thinh Cat, Yang, Jeongsik, Lee, Sang-Oh
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US14/495,183
• Publication Number:
  US 20160087783A1
• Time in Patent Office: 615 Days
• Field of Search: 375/219, 375/220, 375/222, 375/226, 375/257, 375259-261, 375/268, 375/269, 375/275, 375279-281, 375/283, 375/354, 375/356, 375/362, 375/364, 375/375, 327/3, 327/7, 327/8, 327/12, 327 40- 43, 327 63- 65, 327/69, 327/71, 327/72, 327/74, 327/75, 327/77, 327/90, 327/93, 327/144, 327/145, 327231-236, 331/18, 331/25, 340/12.11, 340/12.13, 340/12.51
• US Class Current: 1/1
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 5/22 Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral indicating phase difference of two cyclic pulse trains G01R25/00
• CPC Class Codes: H03M 1/34 Analogue value compared with reference values H03M1/48 takes precedence
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 27/00 Modulated-carrier systems

Abstract

Certain aspects of the present invention provide methods and apparatus for detecting phase shift between signals, such as local oscillating signals in adjacent transceiver paths. One example circuit for phase detection generally includes a mixer configured to mix a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first and second frequencies; a filter connected with the mixer and configured to remove one of the frequency components at the sum of the first and second frequencies, thereby leaving a DC component; and an analog-to-digital converter (ADC) (e.g., a comparator) connected with the filter and configured to determine whether the first input signal is in-phase or out-of-phase with the second input signal based on a comparison between the DC component and a reference signal.

Claims

1. A circuit for phase detection, comprising:

a mixer configured to mix a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first frequency and the second frequency, wherein the first frequency is the same as the second frequency;

a filter connected with the mixer and configured to remove one of the frequency components at the sum of the first frequency and the second frequency, thereby leaving a direct current (DC) component; and

an analog-to-digital converter (ADC) connected with the filter and configured to determine whether the first input signal is in-phase or out-of-phase with the second input signal based on a comparison between the DC component and a reference signal.

2. The circuit of claim 1, wherein the first, second, and output signals are differential signals.

3. The circuit of claim 2, wherein the filter comprises a capacitor to shunt a first output signal and a second output signal of a differential pair for the output signal to generate a first DC component and a second DC component, respectively.

4. The circuit of claim 3, wherein:

the ADC is a comparator configured to compare the first output signal to the second output signal, the second output signal being the reference signal;

the comparator is configured to output a logic HIGH to indicate that the first input signal is in-phase with the second input signal if the first DC component has a greater amplitude than the second DC component; and

the comparator is configured to output a logic LOW to indicate that the first input signal is out-of-phase with the second input signal if the second DC component has a greater amplitude than the first DC component.

5. The circuit of claim 1, wherein:

a first expected phase shift range corresponding to the first input signal being in-phase with the second input signal leads to an amplitude of the DC component being above a first threshold for the ADC; and

a second expected phase shift range corresponding to the first input signal being out-of-phase with the second input signal leads to the amplitude of the DC component being below a second threshold for the ADC.

6. The circuit of claim 1, wherein the mixer comprises a Gilbert cell.

7. The circuit of claim 1, wherein the ADC comprises a clocked regenerative comparator.

8. The circuit of claim 1, wherein the ADC is a multi-bit ADC configured to provide information in addition to a determination whether the first input signal is in-phase or out-of-phase with the second input signal.

9. The circuit of claim 8, wherein the information indicates a degree to which the first and second input signals are phase shifted.

10. A circuit for wireless communications, comprising:

a first transceiver path having a first local oscillating signal with a first frequency;

a second transceiver path having a second local oscillating signal with a second frequency, wherein the first frequency is the same as the second frequency; and

a first phase detector connected with the first transceiver path and the second transceiver path, wherein the first phase detector comprises;

a first mixer configured to mix the first local oscillating signal with the second local oscillating signal to produce a first output signal having frequency components at the sum of and the difference between the first frequency and the second frequency;

a first filter connected with the first mixer and configured to remove one of the frequency components at the sum of the first frequency and the second frequency, thereby leaving a first direct current (DC) component; and

a first analog-to-digital converter (ADC) connected with the first filter and configured to determine whether the first local oscillating signal is in-phase or out-of-phase with the second local oscillating signal based on a comparison between the first DC component and a first reference signal.

11. The circuit of claim 10, wherein:

the first transceiver path comprises a first frequency divider configured to divide a frequency of a voltage-controlled oscillator (VCO) signal to produce the first local oscillating signal; and

the second transceiver path comprises a second frequency divider configured to divide the frequency of the VCO signal to produce the second local oscillating signal.

12. The circuit of claim 11, further comprising a repeater configured to regenerate the VCO signal, wherein the second frequency divider is configured to produce the second local oscillating signal from the regenerated VCO signal.

13. The circuit of claim 10, further comprising a phase shifter configured to phase shift the first local oscillating signal or the second local oscillating signal if the first ADC determines that the first local oscillating signal is out-of-phase with the second local oscillating signal.

14. The circuit of claim 10, further comprising:

a third transceiver path having a third local oscillating signal with a third frequency, wherein the first frequency is the same as the third frequency; and

a second phase detector connected with the second transceiver path and the third transceiver path, wherein the second phase detector comprises;

a second mixer configured to mix the second local oscillating signal with the third local oscillating signal to produce a second output signal having frequency components at the sum of and the difference between the second frequency and the third frequency;

a second filter configured to;

receive the second output signal produced by the second mixer; and

remove one of the frequency components at the sum of the second frequency and the third frequency, thereby leaving a second DC component; and

a second ADC configured to;

receive the second DC component from the second filter; and

determine whether the second local oscillating signal is in-phase or out-of-phase with the third local oscillating signal based on a comparison between the second DC component and a second reference signal.

15. The circuit of claim 14, wherein:

the first transceiver path comprises a first frequency divider configured to divide a frequency of a voltage-controlled oscillator (VCO) signal to produce the first local oscillating signal;

the second transceiver path comprises a second frequency divider configured to divide the frequency of the VCO signal to produce the second local oscillating signal; and

the third transceiver path comprises a third frequency divider configured to divide the frequency of the VCO signal to produce the third local oscillating signal.

16. The circuit of claim 10, wherein the first local oscillating signal, the second local oscillating signal, and the first output signal are differential signals.

17. The circuit of claim 16, wherein the first filter comprises a capacitor configured to shunt signals of a differential pair for the first output signal to generate the first DC component and a second DC component, respectively.

18. The circuit of claim 17, wherein:

the first ADC is a comparator configured to compare the signals of the differential pair for the first output signal;

the comparator is configured to output a logic HIGH to indicate that the first local oscillating signal is in-phase with the second local oscillating signal if the first DC component has a greater amplitude than the second DC component; and

the comparator is configured to output a logic LOW to indicate that the first local oscillating signal is out-of-phase with the second local oscillating signal if the second DC component has a greater amplitude than the first DC component.

19. The circuit of claim 10, wherein the first mixer comprises a Gilbert cell mixer.

20. The circuit of claim 10, wherein the first ADC comprises a clocked regenerative comparator.

21. The circuit of claim 10, wherein:

the first ADC comprises a multi-bit ADC configured to provide information in addition to a determination whether the first local oscillating signal is in-phase or out-of-phase with the second local oscillating signal; and

the information indicates a degree to which the first and second local oscillating signals are phase shifted.

22. A method for detecting phase shift between signals, comprising:

mixing a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first frequency and the second frequency, wherein the first frequency is the same as the second frequency;

filtering the output signal to remove one of the frequency components at the sum of the first frequency and the second frequency, thereby leaving a direct current (DC) component;

comparing the DC component to a reference signal; and

determining whether the first input signal is in-phase or out-of-phase with the second input signal based on the comparison.

23. The method of claim 22, wherein the first, second, and output signals are differential signals.

24. The method of claim 23, wherein the filtering comprises using a capacitor to shunt a first output signal and a second output signal of a differential pair for the output signal to generate a first DC component and a second DC component, respectively.

25. The method of claim 24, wherein:

the comparing comprises comparing the first output signal to the second output signal, the second output signal being the reference signal;

the first input signal is determined to be in-phase with the second input signal if the first DC component has a greater amplitude than the second DC component; and

the first input signal is determined to be out-of-phase with the second input signal if the second DC component has a greater amplitude than the first DC component.

26. The method of claim 22, wherein:

a first expected phase shift range corresponding to the first input signal being in-phase with the second input signal leads to an amplitude of the DC component being above a first threshold; and

a second expected phase shift range corresponding to the first input signal being out-of-phase with the second input signal leads to the amplitude of the DC component being below a second threshold.

27. The method of claim 22, wherein the mixing comprises using a Gilbert cell to mix the first input signal with the second input signal.

28. The method of claim 22, wherein:

the first input signal is a first local oscillating signal of a first transceiver path; and

the second input signal is a second local oscillating signal of a second transceiver path adjacent to the first transceiver path.

29. The method of claim 28, further comprising:

frequency dividing a voltage-controlled oscillator (VCO) signal to generate the first local oscillating signal;

regenerating the VCO signal to generate a repeated oscillating signal; and

frequency dividing the repeated oscillating signal to generate the second local oscillating signal.

30. The method of claim 22, further comprising phase shifting the first input signal or the second input signal if the first input signal is determined to be out-of-phase with the second input signal.