Synchronous reset and phase detecting for interchain local oscillator (LO) divider phase alignment

• US 9,356,769 B2
• Filed: 02/05/2015
• Issued: 05/31/2016
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, David Ta-Hsiang
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US14/615,002
• Publication Number:
  US 20160087784A1
• Time in Patent Office: 481 Days
• Field of Search: 375/211, 375/215, 375/219, 375/220, 375/222, 375/354, 375/355, 455/39, 455/500, 455/502, 455/73, 455/76, 455/80, 455/88
• US Class Current: 1/1
• CPC Class Codes: H04B 1/0032 with analogue quadrature frequency conversion to and from the baseband quadrature modulators and demodulators per se H03D3/007, H03C3/40
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• CPC Class Codes: H04L 7/0041 Delay of data signal

Abstract

Certain aspects of the present invention provide methods and apparatus for synchronizing frequency-divided oscillating signals associated with multiple radio frequency (RF) paths to be in-phase. For certain aspects, a reset pulse is input to synchronization logic for a particular RF path, and this logic retimes the reset pulse to a local synthesizer clock in this RF path. The retimed reset pulse drives the reset input of a local frequency divider for this RF path and is also appropriately delayed, buffered, and then daisy-chained to the synchronization logic in the next RF path to be repeated therein. By appropriately resetting the local frequency dividers using the synchronization logic in this manner, the frequency-divided oscillating signals for the RF paths are synchronized to operate in-phase with one another.

Claims

1. A method for synchronizing frequency-divided oscillating signals associated with multiple transceiver paths to be in-phase, the method comprising:

providing a first oscillating signal for a first transceiver path;

receiving a first global reset signal;

delaying the first global reset signal by clocking with the first oscillating signal to generate a first local reset signal synchronized to the first oscillating signal;

frequency dividing the first oscillating signal to generate a first frequency-divided signal for the first transceiver path, wherein the first local reset signal resets the frequency dividing of the first oscillating signal;

outputting a second global reset signal synchronized to the first oscillating signal;

providing a second oscillating signal for a second transceiver path, wherein the second oscillating signal has the same frequency as the first oscillating signal;

delaying the second global reset signal by clocking with the second oscillating signal to generate a second local reset signal synchronized to the second oscillating signal; and

frequency dividing the second oscillating signal to generate a second frequency-divided signal for the second transceiver path, wherein the second local reset signal resets the frequency dividing of the second oscillating signal such that the second frequency-divided signal is in phase with the first frequency-divided signal.

2. The method of claim 1, further comprising generating a synthesized oscillating signal from a frequency synthesizer, wherein the first oscillating signal is based on the synthesized oscillating signal.

3. The method of claim 2, wherein providing the first oscillating signal comprises buffering the synthesized oscillating signal.

4. The method of claim 2, wherein providing the first oscillating signal comprises regenerating the synthesized oscillating signal, or a regenerated version thereof, from a third transceiver path.

5. The method of claim 2, wherein receiving the first global reset signal is in response to the frequency synthesizer starting up or changing one or more operating parameters.

6. The method of claim 1, wherein receiving the first global reset signal comprises receiving the first global reset signal from a third transceiver path and wherein the first global reset signal is synchronized to a third oscillating signal for the third transceiver path.

7. The method of claim 1, further comprising deriving the second oscillating signal from the first oscillating signal.

8. The method of claim 1, wherein outputting the second global reset signal comprises delaying the first global reset signal by clocking with the first oscillating signal a multiple of a least common multiple (LCM) between divisor options for the frequency dividing of the first oscillating signal, wherein the divisor options are 2 and 3, wherein the LCM is 6, and wherein the first global reset signal is delayed 6 times by clocking 6 cascaded delay (D) flip-flops with the first oscillating signal.

9. The method of claim 1, further comprising:

outputting a third global reset signal synchronized to the second oscillating signal;

providing a third oscillating signal for a third transceiver path, wherein the third oscillating signal has the same frequency as the first oscillating signal and the second oscillating signal;

delaying the third global reset signal by clocking with the third oscillating signal to generate a third local reset signal synchronized to the third oscillating signal; and

frequency dividing the third oscillating signal to generate a third frequency-divided signal for the third transceiver path, wherein the third local reset signal resets the frequency dividing of the third oscillating signal such that the third frequency-divided signal is in phase with the first frequency-divided signal and the second frequency-divided signal.

10. The method of claim 1, wherein frequency dividing the first oscillating signal comprises dividing a frequency of the first oscillating signal by 3.

11. A circuit for synchronizing frequency-divided oscillating signals associated with multiple transceiver paths to be in-phase, the circuit comprising:

a first distribution circuit configured to provide a first oscillating signal for a first transceiver path;

first synchronization logic configured to;

receive a first global reset signal;

delay the first global reset signal by clocking with the first oscillating signal to generate a first local reset signal synchronized to the first oscillating signal; and

output a second global reset signal synchronized to the first oscillating signal;

a first frequency divider configured to frequency divide the first oscillating signal to generate a first frequency-divided signal for the first transceiver path, wherein the first local reset signal is configured to reset the first frequency divider;

a second distribution circuit configured to provide a second oscillating signal for a second transceiver path, wherein the second oscillating signal has the same frequency as the first oscillating signal;

second synchronization logic configured to delay the second global reset signal by clocking with the second oscillating signal to generate a second local reset signal synchronized to the second oscillating signal; and

a second frequency divider configured to frequency divide the second oscillating signal to generate a second frequency-divided signal for the second transceiver path, wherein the second local reset signal is configured to reset the second frequency divider such that the second frequency-divided signal is in phase with the first frequency-divided signal.

12. The circuit of claim 11, further comprising a frequency synthesizer configured to generate a synthesized oscillating signal, wherein the first oscillating signal is based on the synthesized oscillating signal.

13. The circuit of claim 12, wherein the first distribution circuit comprises a buffer configured to buffer the synthesized oscillating signal to provide the first oscillating signal.

14. The circuit of claim 12, wherein the first distribution circuit comprises a repeater configured to regenerate the synthesized oscillating signal, or a regenerated version thereof, from a third transceiver path.

15. The circuit of claim 12, wherein the first synchronization logic is configured to receive the first global reset signal in response to the frequency synthesizer starting up or changing one or more operating parameters.

16. The circuit of claim 11, wherein the first synchronization logic is configured to receive the first global reset signal from a third transceiver path and wherein the first global reset signal is synchronized to a third oscillating signal for the third transceiver path.

17. The circuit of claim 11, wherein the first synchronization logic is configured to output the second global reset signal by delaying the first global reset signal via clocking with the first oscillating signal a multiple of a least common multiple (LCM) between divisor options for the first frequency divider, wherein the divisor options are 2 and 3, wherein the LCM is 6, and wherein the first global reset signal is delayed 6 times by clocking 6 cascaded delay (D) flip-flops with the first oscillating signal.

18. The circuit of claim 11, wherein the first frequency divider is configured to divide a frequency of the first oscillating signal by at least one of 2 or 3.

19. An apparatus for synchronizing frequency-divided oscillating signals associated with multiple transceiver paths to be in-phase, the apparatus comprising:

means for providing a first oscillating signal for a first transceiver path;

means for receiving a first global reset signal;

means for delaying the first global reset signal by clocking with the first oscillating signal to generate a first local reset signal synchronized to the first oscillating signal;

means for frequency dividing the first oscillating signal to generate a first frequency-divided signal for the first transceiver path, wherein the first local reset signal is configured to reset the means for frequency dividing the first oscillating signal;

means for outputting a second global reset signal synchronized to the first oscillating signal;

means for providing a second oscillating signal for a second transceiver path, wherein the second oscillating signal has the same frequency as the first oscillating signal;

means for delaying the second global reset signal by clocking with the second oscillating signal to generate a second local reset signal synchronized to the second oscillating signal; and

means for frequency dividing the second oscillating signal to generate a second frequency-divided signal for the second transceiver path, wherein the second local reset signal is configured to reset the means for frequency dividing the second oscillating signal such that the second frequency-divided signal is in phase with the first frequency-divided signal.