Methods and systems for chip-to-chip communication with reduced simultaneous switching noise
First Claim
Patent Images
1. A method comprising:
- receiving a set of input bits representing information;
mapping, using an encoder, values to a set of wires, the values corresponding to elements of a transmit codeword of a vector signaling code, wherein at least one value is mapped by assigning the value to a corresponding wire having a wire position index determined by a logical combination of at least two of the input bits; and
,transmitting, using a plurality of line drivers, the values on the set of wires.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
-
Citations
20 Claims
-
1. A method comprising:
-
receiving a set of input bits representing information; mapping, using an encoder, values to a set of wires, the values corresponding to elements of a transmit codeword of a vector signaling code, wherein at least one value is mapped by assigning the value to a corresponding wire having a wire position index determined by a logical combination of at least two of the input bits; and
,transmitting, using a plurality of line drivers, the values on the set of wires. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An apparatus comprising:
-
an encoder configured to receive a set of input bits and to responsively map values to a set of wires, the values corresponding to elements of a transmit codeword of a vector signaling code, wherein at least one value is mapped by assigning the value to a corresponding wire having a wire position index determined by a logical combination of at least two of the input bits; and
,a plurality of line drivers to transmit the values on the set of wires. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification