Software indications and hints for coalescing memory transactions

• US 9,361,031 B2
• Filed: 09/15/2015
• Issued: 06/07/2016
• Est. Priority Date: 12/12/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Gschwind, Michael Karl, Salapura, Valentina, Shum, Chung-Lung K.
• Primary Examiner(s): YU, JAE UN
• Application Number:
  US14/854,473
• Publication Number:
  US 20160004461A1
• Time in Patent Office: 266 Days
• Field of Search: 711/147
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

A transactional memory system that utilizes indications for the coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction a processor of the transactional memory system executes one or more coalescing instructions for controlling coalescing of a plurality of outermost transactions. Based on the execution of the one or more coalescing instructions, the processor determines whether two outermost transactions are to be coalesced. Based on determining that two outermost transactions are to be coalesced, the processor coalesces at least two outermost transactions included in the plurality of outermost transactions.

Claims

1. A method of utilizing indications for coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising:

executing, by a processor, one or more coalescing instructions for controlling coalescing of a plurality of outermost transactions;

based on the execution of the one or more coalescing instructions, determining, by the processor, whether two outermost transactions are to be coalesced based, at least in part, on i) a threshold value that is set based, at least in part, on the one or more coalescing instructions that are executed, and ii) a determination of whether a coalescing of the two outermost transactions will exceed the threshold value, wherein coalescing of a given outermost transaction is disabled for that particular outermost transaction based on a determination that coalescing will exceed a threshold value that is configured to assess, at least in part, a characteristic of at least one of the plurality of outermost transactions; and

based on determining two outermost transactions are to be coalesced, coalescing, by the processor, at least two outermost transactions included in the plurality of outermost transactions.

2. The method of claim 1, wherein the one or more coalescing instructions, when executed, indicate which outermost transactions can be coalesced.

3. The method of claim 1, wherein the one or more coalescing instructions include one or both of a coalescing prefix that is associated with a transaction begin instruction of an outermost transaction and a coalescing argument associated with a transaction begin instruction of an outermost transaction.

4. The method of claim 1, wherein the one or more coalescing instructions include one or both of a coalescing prefix that is associated with a transaction end instruction of an outermost transaction and a coalescing argument associated with the transaction end instruction of an outermost transaction.

5. The method of claim 1, the method further comprising:

executing, by the processor, a set-transaction-coalesce-mode (STCM) instruction the STCM instruction causing the processor to enter STCM mode, wherein entering STCM mode indicates at least one of (i) that subsequent coalescing instructions are enabled to cause transactions to-be coalesced, (ii) a maximum number of instructions that can be present between two outermost transactions to be coalesced, and (iii) a type of instructions that can be present between two outermost transactions to be coalesced.

6. The method of claim 1, the method further comprising:

executing a reset-transaction-coalesce-mode (RTCM) instruction, the RTCM instruction causing the processor to exit STCM mode, wherein exiting STCM mode results in one or more of (i) a cessation of execution of subsequent coalescing instructions, (ii) a modification of a number of instructions that exists between two outermost transactions, and (iii) a modification of a type of instruction that exists between two outermost transactions.

7. The method of claim 1, wherein coalescing of a given outermost transaction is disabled for that particular outermost transaction based on determining that coalescing will exceed a threshold value that indicates any one of:

a stall being exhibited by an outermost transaction to be coalesced, a maximum number of instructions that can exist between two outermost transactions to be coalesced, a maximum time period required to process outermost transactions that are coalesced, a quantity of resources that are required to process outermost transactions that are coalesced, a maximum number of outermost transactions that can be coalesced, a number of allowable instances of coalescing that particular outermost transaction that lead to an abort status, and a history of coalesced transactions that previously experienced an abort.