SMS4 acceleration processors, methods, systems, and instructions

• US 9,361,106 B2
• Filed: 12/27/2013
• Issued: 06/07/2016
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert M., Gopal, Vinodh, Yap, Kirk S., Feghali, Wajdi K.
• Primary Examiner(s): Armouche, Hadi
• Assistant Examiner(s): STEINLE, ANDREW J
• Application Number:
  US14/142,724
• Publication Number:
  US 20150186138A1
• Time in Patent Office: 893 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms

Abstract

A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

Claims

1. A processor comprising:

a plurality of packed data registers;

a decoder to decode an instruction, the instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SMS4 rounds, and a 32-bit value; and

an execution unit including at least some circuitry coupled with the decoder and coupled with the plurality of the packed data registers, the execution unit, in response to the instruction, to store a 32-bit result of a current SMS4 round in a destination packed data register of the plurality of packed data registers that is to be indicated by the instruction.

2. The processor of claim 1, in which the decoder is to decode the instruction in which the four 32-bit results are to include four 32-bit results of four prior SMS4 encryption rounds and in which the 32-bit value is to include a 32-bit round key for a current SMS4 encryption round, and in which the execution unit is to store the 32-bit result which is to include a 32-bit result of a current SMS4 encryption round.

3. The processor of claim 1, in which the decoder is to decode the instruction in which the four 32-bit results are to include four 32-bit round keys for four prior SMS4 key expansion rounds and in which the 32-bit value is to include a 32-bit constant to be input to a current SMS4 key expansion round, and in which the execution unit is to store the 32-bit result which is to include a 32-bit round key of a current SMS4 key expansion round.

4. The processor of claim 1, in which the decoder is to decode the instruction that is to have one or more bits to specify whether the current SMS4 round is an SMS4 key expansion round or an SMS4 encryption or decryption round.

5. The processor of claim 4, in which the instruction is to have a single bit to specify whether the current SMS4 round is the SMS4 key expansion round or the SMS4 encryption or decryption round.

6. The processor of claim 1, in which the decoder is to decode the instruction that is to indicate a 128-bit source packed data operand that is to have the four 32-bit results of the four prior SMS4 rounds.

7. The processor of claim 6, in which the 128-bit source packed data operand is to have the four 32-bit results of the four prior SMS4 rounds arranged according to round order.

8. The processor of claim 1, in which the execution unit is to store the 32-bit result of the current SMS4 round in a result packed data that is also to include three of the four 32-bit results from three immediately prior SMS4 rounds of the four prior SMS4 rounds.

9. The processor of claim 8, in which the result packed data is to have each of the three 32-bit results from the three immediately prior SMS4 rounds each shifted by one 32-bit position relative to a corresponding bit position in which they appear in a source operand.

10. The processor of claim 1, in which the decoder is to decode the instruction that is to indicate a source packed data operand that is to have,

a first 32-bit result of an immediately prior SMS4 round in bits [31:

0],

a second 32-bit result of a second prior SMS4 round in bits [63;

32],

a third 32-bit result of a third prior SMS4 round in bits [95;

64], and

a fourth 32-bit result of a fourth prior SMS4 round in bits [127;

96].

11. The processor of claim 10, in which the execution unit is to store a result packed data that is to include,

the 32-bit result of the current SMS4 round in bits [31:

0],

the first 32-bit result of the immediately prior SMS4 round in bits [63;

32],

the second 32-bit result of the second prior SMS4 round in bits [95;

64], and

the third 32-bit result of the third prior SMS4 round in bits [127;

96].

12. A method in a processor comprising:

receiving an instruction at a decoder of the processor and decoding the instruction with the decoder, the instruction indicating one or more source packed data operands, the one or more source packed data operands having four 32-bit results of four prior SMS4 rounds, and a 32-bit value; and

storing, with an execution unit of the processor, a 32-bit result of a current SMS4 round in a destination storage location in response to the instruction, the destination storage location indicated by the instruction.

13. The method of claim 12, in which receiving comprises receiving the instruction in which the four 32-bit results include four 32-bit results of four prior SMS4 encryption rounds and in which the 32-bit value includes a 32-bit round key for a current SMS4 encryption round, and in which the storing comprises storing the 32-bit result that includes a 32-bit result of a current SMS4 encryption round.

14. The method of claim 12, in which receiving comprises receiving the instruction in which the four 32-bit results include four 32-bit round keys for four prior SMS4 key expansion rounds and in which the 32-bit value includes a 32-bit constant to be input to a current SMS4 key expansion round, and in which the storing comprises storing the 32-bit result that includes a 32-bit round key of a current SMS4 key expansion round.

15. The method of claim 12, in which receiving comprises receiving the instruction that has one or more bits specifying whether the current SMS4 round is an SMS4 key expansion round or an SMS4 encryption or decryption round.

16. The method of claim 12, in which receiving comprises receiving the instruction that indicates a 128-bit source packed data operand that has the four 32-bit results of the four prior SMS4 rounds arranged according to round order.

17. The method of claim 12, in which storing comprises storing the 32-bit result of the current SMS4 round in a result packed data that also includes three of the four 32-bit results from three immediately prior SMS4 rounds of the four prior SMS4 rounds.

18. The method of claim 12, in which receiving comprises receiving the instruction that indicates a source packed data operand that has,

a first 32-bit result of an immediately prior SMS4 round in bits [31:

0],

a second 32-bit result of a second prior SMS4 round in bits [63;

32],

a third 32-bit result of a third prior SMS4 round in bits [95;

64], and

a fourth 32-bit result of a fourth prior SMS4 round in bits [127;

96].

19. The method of claim 18, in which storing comprises storing a result packed data that includes,

the 32-bit result of the current SMS4 round in bits [31:

0],

the first 32-bit result of the immediately prior SMS4 round in bits [63;

32],

the second 32-bit result of the second prior SMS4 round in bits [95;

64], and

the third 32-bit result of the third prior SMS4 round in bits [127;

96].

20. A system to process instructions comprising:

an interconnect;

a processor coupled with the interconnect, the processor to receive a first SMS acceleration instruction, the first SMS acceleration instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SMS4 rounds, and a 32-bit value, the processor including a decoder to decode the first SMS acceleration instruction, and the processor, in response to the first SMS acceleration instruction, to store, with an execution unit of the processor, a result packed data including a 32-bit result of a current SMS4 round in a destination packed data register of the processor that is to be indicated by the first SMS acceleration instruction; and

a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing an SMS4 algorithm, the SMS4 algorithm including a second SMS acceleration instruction that indicates the result packed data as a source packed data operand.

21. The system of claim 20, wherein the result packed data has three 32-bit results of three immediately prior rounds, and wherein the 32-bit results in the result packed data are arranged in round order.

22. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing an instruction,

the instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SMS4 rounds, and a 32-bit value, and the instruction if performed by a machine that includes a decoder to decode the instruction is operable to cause the machine to perform operations comprising:

storing a 32-bit result of a current SMS4 round in a destination packed data register of the machine that is to be indicated by the instruction.

23. The article of claim 22, wherein the 32-bit result is to be stored in a result packed data along with three 32-bit results corresponding to three immediately prior rounds.