Virtualization across physical partitions of a multi-core processor (MCP)

• US 9,361,160 B2
• Filed: 05/19/2014
• Issued: 06/07/2016
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated (Kyndryl Holdings, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Duvalsaint, Karl J., Hofstee, Harm P., Kim, Daeik, Kim, Moon J.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/281,062
• Publication Number:
  US 20140259013A1
• Time in Patent Office: 750 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A generic microprocessor architecture is provided with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Claims

1. A multi-core processor, comprising:

a set of main processing elements, each configured to request a set of sub-processing elements from a logical group of sub-processing elements, the set of main processing elements comprising;

a first main processing element located in a first physical partition,

a second main processing element located in a second physical partition, and

a third main processing element located in a third physical partition,

wherein the logical group of sub-processing elements comprises;

a first sub-processing element located in the first physical partition,

a second sub-processing element located in the second physical partition, and

a third sub-processing element located in the third physical partition; and

a first virtualized control thread generated by the first main processing element, the first virtualized control thread associating the second main processing element of the second physical partition with the logical group of sub-processing elements;

wherein each of the first main processing element, the second main processing element, and the third main processing element, is configured to log events taking place at each of the first sub-processing element, the second sub-processing element, and the third sub-processing element.

2. The multi-core processor of claim 1, further comprising a second virtualized control thread generated by the second main processing element, the second virtualized control thread associating the second main processing element with a group of sub-processing elements.

3. The multi-core processor of claim 2, the group of sub-processing elements being in the second physical partition.

4. The multi-core processor of claim 2, the group of sub-processing elements being in the third physical partition.

5. The multi-core processor of claim 1, further comprising a first logical partition, the first logical partition comprising all sub-processing elements in the first physical partition.

6. The multi-core processor of claim 1, further comprising a first logical partition, the first logical partition comprising only a subset of all sub-processing elements in the first physical partition.

7. The multi-core processor of claim 5, the first virtualized control thread being configured to send program code and data to the sub-processing elements of the first logical partition.

8. The multi-core processor of claim 6, the first virtualized control thread being further configured to collect computation results from the sub-processing elements of the first logical partition.

9. The multi-core processor of claim 5, the first virtualized control thread controlling a clock speed, power consumption and computation loading of the sub-processing elements of the first logical partition.

10. A multi-core processor, comprising:

a first physical partition comprising a first main processing element, and a first group of sub-processing elements;

a second physical partition comprising a second main processing element, and a second group of sub-processing elements;

a third physical partition comprising a third main processing element, and a third group of sub-processing elements;

a logical partition comprising the first group of sub-processing elements, the second group of sub-processing elements, and the third group of sub-processing elements; and

a virtualized control thread generated by the first main processing element, the virtualized control thread being configured to associate the second main processing element of the second physical partition with the logical partition, and the virtualized control thread being configured to control sub-processing elements of the logical partition;

wherein each of the first main processing element, the second main processing element, and the third main processing element, is configured to log events taking place at each of the first sub-processing element, the second sub-processing element, and the third sub-processing element.

11. The multi-core processor of claim 10, the virtualized control thread extending across physical boundaries defined by the first physical partition, the second physical partition, and the third physical partition.

12. The multi-core processor of claim 10, the virtualized control thread being configured to send program code and data to the sub-processing elements of the logical partition.

13. The multi-core processor of claim 10, the virtualized control thread being further configured to collect computation results from the sub-processing elements of the logical partition.

14. The multi-core processor of claim 10, the virtualized control thread controlling a clock speed of the logical partition.

15. The multi-core processor of claim 10, the virtualized control thread controlling a power consumption of the partition.

16. The multi-core processor of claim 10, the virtualized control thread controlling a computation loading of the sub-processing elements of the logical partition.

17. A processing method, comprising:

receiving a request, issued from a main processing element, for a number of sub-processing elements, the main processing element located within a first physical partition;

determining that the requested number of sub-processing elements exceeds a number of free sub-processing elements within the first physical partition;

locating at least two available sub-processing elements, at least one of the at least two available sub-processing elements located in a second physical partition, and at least one other of the at least two available sub-processing elements located in a third physical partition;

joining free sub-processing elements of the first physical partition with the at least two available sub-processing elements into a logical partition;

associating the main processing element with the logical partition, a virtualized control thread being generated by the main processing element;

controlling a group of sub-processing elements of the logical partition using the virtualized control thread; and

logging, by the main processing element, events taking place at each of the sub-processing elements.

18. The processing method of claim 17, the virtualized control thread being in the first physical partition, and the logical partition being in the first physical partition.

19. The processing method of claim 17, the virtualized control thread being in the second physical partition, and the logical partition being in the first physical partition.

20. The processing method of claim 17, the virtualized control thread being in the first physical partition and the logical partition being in the second physical partition.