Dynamic reservations in a unified request queue
First Claim
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1. An integrated circuit, comprising:
- a substrate;
circuitry fabricated on the substrate, wherein the circuitry includes a memory controller including;
a unified request queue including a total of N entries, wherein N is a positive integer greater than one and any of the N entries is allocable to a request of any of multiple request types; and
control logic that reserves a number of entries in the unified request queue for a first request type among the multiple request types and that dynamically varies the number of entries reserved for the first request type based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests, wherein the control logic dynamically varies the number of entries reserved for the first request type based on a number of Retry coherence responses provided for requests of the first request type within a predetermined period.
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Abstract
A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally allocable to requests of any of the multiple request types. A number of entries in the unified request queue is reserved for a first request type among the multiple types of requests. The number of entries reserved for the first request type is dynamically varied based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests.
19 Citations
19 Claims
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1. An integrated circuit, comprising:
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a substrate; circuitry fabricated on the substrate, wherein the circuitry includes a memory controller including; a unified request queue including a total of N entries, wherein N is a positive integer greater than one and any of the N entries is allocable to a request of any of multiple request types; and control logic that reserves a number of entries in the unified request queue for a first request type among the multiple request types and that dynamically varies the number of entries reserved for the first request type based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests, wherein the control logic dynamically varies the number of entries reserved for the first request type based on a number of Retry coherence responses provided for requests of the first request type within a predetermined period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 11)
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9. A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a memory controller for controlling access to a system memory at a lowest level of a volatile memory hierarchy of the data processing system, the memory controller including; a unified request queue including a total of N entries, wherein N is a positive integer greater than one and any of the N entries is allocable to a request of any of multiple request types; and control logic that reserves a number of entries in the unified request queue for a first request type among the multiple request types and that dynamically varies the number of entries reserved for the first request type based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests, wherein the control logic dynamically varies the number of entries reserved for the first request type based on a number of Retry coherence responses provided for requests of the first request type within a predetermined period. - View Dependent Claims (10, 12, 13, 14, 15, 16, 17, 18, 19)
Specification