Multi-channel, multi-bank memory with wide data input/output

• US 9,361,973 B2
• Filed: 03/28/2014
• Issued: 06/07/2016
• Est. Priority Date: 10/28/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Maheshwari, Dinesh
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/228,899
• Publication Number:
  US 20150117091A1
• Time in Patent Office: 802 Days
• Field of Search: 365/154, 365/189.05, 365/189.03, 365/189.18, 710/305
• US Class Current: 1/1
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/2209 Concurrent read and write
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal.

Claims

1. An integrated circuit (IC) device, comprising:

M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value;

N channels, where N is greater than 2, and each channel includes its own data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal, and wherein each channel is configured to transfer greater than one bit on each read or write access; and

a controller subsystem configured to control accesses between each channel of the N channels and each memory bank of the M memory banks, and wherein the controller subsystem is configured to control a first access on every channel of the N channels during a first cycle of the clock signal, wherein each access of the first access on every channel is responsive to a different memory address, and control a second access on every channel of the N channels during a second cycle of the clock signal wherein the first cycle and the second cycle are consecutive cycles of the clock signal.

2. The IC device of claim 1, wherein:

M is no less than 8.

3. The IC device of claim 1, wherein:

each bank includes a plurality of static random access memory cells.

4. The IC device of claim 1, wherein:

N is no less than 8.

5. The IC device of claim 1, wherein:

the data connections of each channel include no less than 32 bi-directional data connections.

6. The IC device of claim 1, wherein:

the controller subsystem includes a cross-bar circuit configurable to enable a data access between any channel and any bank.

7. The IC device of claim 1, wherein:

the controller subsystem includes

a write cache partitioned into write data buffers corresponding to each bank, and

data forwarding logic configured to forward a most recently received write data value for a bank as read data from the bank.

8. An integrated circuit (IC) device, comprising:

M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value;

N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control inputs connections for executing a read or write access to one of the memory banks, wherein each channel is configured to transfer greater than four bits per clock cycle; and

a controller subsystem configured to enable accesses between each channel of the N channels and each memory bank of the M memory banks.

9. The IC device of claim 8, wherein:

the controller subsystem enables accesses up to an access on every channel on consecutive cycles of a clock signal.

10. The IC device of claim 8, wherein:

the data connections of the N channels are configured as double data rate connections, latching write data on in synchronism with rising and falling edges of a periodic clock and outputting read data on in synchronism with rising and falling edges of the periodic clock.

11. The IC device of claim 8, wherein:

the controller subsystem includes a circuit operable to connect at least address data from every channel to address decoders within every memory bank.

12. The IC device of claim 8, wherein:

the controller subsystem includes

a write cache partitioned into write data buffers corresponding to each bank, and

data forwarding logic configured to forward a most recently received write data value for an address of a bank as read data to the address of the bank.

13. The IC device of claim 8, wherein:

M is no less than 8; and

N is no less than 8.

14. The IC device of claim 8, wherein:

each memory bank is subdivided into plurality of slices, each slice including a plurality of uni-directional read data lines configured to output read data from memory cells of the slice and uni-directional write data lines configured to receive write data from one of the channels.