Flash-based memory system with robust backup and restart features and removable modules
First Claim
1. A Flash-based memory system having a backup power source, comprising:
- a printed circuit board (PCB);
a plurality of Flash memory devices mounted to the PCB, each Flash memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings;
a Flash controller mounted to the PCB and communicating independently with each Flash memory device to perform the memory operations;
a power circuit mounted to the PCB and providing power to the Flash memory devices, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device; and
a central processing unit (CPU) mounted to the PCB and coupled to the power circuit and the Flash controller, the CPU configured to perform one or more test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising;
disabling the charging circuitry from charging the charge storage device;
obtaining a first voltage measurement from the charge storage device;
applying a predefined load to the charge storage device;
obtaining a second voltage measurement from the charge storage device;
waiting a predefined amount of time; and
obtaining a third voltage measurement from the charge storage device;
wherein the CPU provides an indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements.
1 Assignment
0 Petitions
Accused Products
Abstract
A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.
-
Citations
20 Claims
-
1. A Flash-based memory system having a backup power source, comprising:
-
a printed circuit board (PCB); a plurality of Flash memory devices mounted to the PCB, each Flash memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings; a Flash controller mounted to the PCB and communicating independently with each Flash memory device to perform the memory operations; a power circuit mounted to the PCB and providing power to the Flash memory devices, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device; and a central processing unit (CPU) mounted to the PCB and coupled to the power circuit and the Flash controller, the CPU configured to perform one or more test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising; disabling the charging circuitry from charging the charge storage device; obtaining a first voltage measurement from the charge storage device; applying a predefined load to the charge storage device; obtaining a second voltage measurement from the charge storage device; waiting a predefined amount of time; and obtaining a third voltage measurement from the charge storage device; wherein the CPU provides an indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method of testing a Flash-based memory system having a backup power source, comprising:
-
providing power to the Flash-based memory system, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device; automatically performing one or more test procedures on the charge storage device and providing an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising; disabling the charging circuitry from charging the charge storage device; obtaining a first voltage measurement from the charge storage device; applying a predefined load to the charge storage device; obtaining a second voltage measurement from the charge storage device; waiting a predefined amount of time; and obtaining a third voltage measurement from the charge storage device; wherein providing an indication of the charge storage capacity of the charge storage device comprises providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A Flash-based memory system having a backup power source, comprising:
-
a plurality of Flash memory devices; a Flash controller communicating independently with each Flash memory device; a backup power source providing power to the Flash memory devices when a primary power source falls below a predefined level, the backup power source including a charge storage device; and a central processing unit (CPU) coupled to the backup power source, the CPU configured to perform one or more predefined test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the CPU providing the indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device; wherein the CPU is configured to provide the capacitance C and the ESR of the charge storage device using one or more predefined equations involving voltage measurements from the charge storage device, a predefined load, and a predefined amount of time, wherein the one or more test procedures comprising; disabling the charging circuitry from charging the charge storage device; obtaining a first voltage measurement from the charge storage device; applying a predefined load to the charge storage device; obtaining a second voltage measurement from the charge storage device; waiting a predefined amount of time; and obtaining a third voltage measurement from the charge storage device. - View Dependent Claims (18, 19, 20)
-
Specification