Method of reducing hot electron injection type of read disturb in memory

• US 9,361,993 B1
• Filed: 01/21/2015
• Issued: 06/07/2016
• Est. Priority Date: 01/21/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Dong, Yingda, Zhao, Wei, Kwong, Charles
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/601,531
• Time in Patent Office: 503 Days
• Field of Search: 36518501-18533
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem

Abstract

Read disturb is reduced in a charge-trapping memory device such as a 3D memory device by optimizing the channel boosting voltage in an unselected NAND string. A pass voltage applied to the unselected word lines can cause a large gradient in the channel which leads to electron-hole formation and a hot electron injection (HEI) type of read disturb. When the selected word line is close to the source-side of the NAND string, HEI disturb occurs on the drain-side of the selected word line. To avoid this disturb, a spike is provided in the control gate voltage of a drain-side selected gate transistor to temporarily connect the channel to the bit line, lowering the voltage of the associated channel region. A similar approach is used for a drain-side selected word line. The spike may be omitted when the selected word line is mid-range.

Claims

1. A method for performing a sensing operation in a non-volatile memory device, the method comprising:

performing a boosting phase of the sensing operation, the boosting phase sets a boosting voltage of a channel of an unselected NAND string in the memory device, the unselected NAND string comprising a drain-end select gate at a drain-end of the unselected NAND string and a source-end select gate at a source-end of the unselected NAND string;

after the boosting voltage is set, performing a sensing phase of the sensing operation, the sensing phase senses a current in a selected NAND string of the memory device, the selected NAND string comprising a drain-end select gate at a drain-end of the selected NAND string and a source-end select gate at a source-end of the selected NAND string;

wherein;

the memory device comprises multiple word lines of memory cells including a selected word line and unselected word lines;

the selected NAND string and the unselected NAND strings each comprise a charge-trapping layer and a polysilicon channel layer which extend vertically in a three-dimensional stacked memory structure; and

during the sensing phase, the current is sensed via a bit line which is connected to the drain-end of the selected NAND string and the drain-end of the unselected NAND string while one or more read voltages are applied to the selected word line;

wherein the performing the boosting phase comprises;

applying an increasing voltage to the unselected word lines;

if the selected word line is at a source-side of the unselected NAND string, controlling the drain-end select gate of the unselected NAND string to, at different times during the applying of the increasing voltage, allow a driven voltage on the bit line to reach the channel of the unselected NAND string by providing the drain-end select gate of the unselected NAND string in a conductive state and prevent the driven voltage on the bit line from reaching the channel of the unselected NAND string by providing the drain-end select gate of the unselected NAND string in a non-conductive state;

if the selected word line is at a drain-side of the unselected NAND string, controlling the source-end select gate of the unselected NAND string to, at different times during the applying of the increasing voltage, allow a driven voltage on a source line to reach the channel of the unselected NAND string by providing the source-end select gate of the unselected NAND string in a conductive state and prevent the driven voltage on the source line from reaching the channel of the unselected NAND string by providing the source-end select gate of the unselected NAND string in a non-conductive state; and

if the selected word line is midrange between the drain-end of the unselected NAND string and the source-end of the unselected NAND string, preventing the driven voltage on the bit line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage by providing the drain-end select gate of the unselected NAND string in a non-conductive state, and preventing the driven voltage on the source line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage by providing the source-end select gate of the unselected NAND string in a non-conductive state.

2. The method of claim 1, wherein:

the selected word line is midrange between the drain-end of the unselected NAND string and the source-side of the unselected NAND string when the selected word line is among a subset of the multiple word lines which is centered between the drain-end of the unselected NAND string and the source-end of the unselected NAND string, the subset comprising up to 20% of the multiple word lines.

3. The method of claim 1, further comprising:

if the selected word line is at the source-side of the unselected NAND string, providing memory cells connected to the selected word line in a conductive state while the driven voltage on the bit line is allowed to reach the channel of the unselected NAND string; and

if the selected word line is at the drain-side of the unselected NAND string, providing the memory cells connected to the selected word line in the conductive state while the driven voltage on the source line is allowed to reach the channel of the unselected NAND string.

4. The method of claim 1, further comprising:

if the selected word line is at the source-side of the unselected NAND string, providing the source-end select gate of the unselected NAND string in a non-conductive state to prevent the driven voltage on the source line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage.

5. The method of claim 1, further comprising:

if the selected word line is at the drain-side of the unselected NAND string, providing the drain-end select gate of the unselected NAND string in a non-conductive state to prevent the driven voltage on the bit line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage.

6. The method of claim 1, wherein:

the selected word line is at the source-side of the unselected NAND string when the selected word line is among a source-side subset of the multiple word lines which is adjacent to the source-end of the unselected NAND string, the source-side subset comprising up to 40% of the multiple word lines; and

the selected word line is at the drain-side of the unselected NAND string when the selected word line is among a drain-side subset of the multiple word lines which is adjacent to the drain-end of the unselected NAND string, the drain-side subset comprising up to 40% of the multiple word lines.

7. The method of claim 1, wherein:

if the selected word line is at the source-side of the unselected NAND string, the driven voltage on the bit line is allowed to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is inversely proportional to a distance of the selected word line from the source-end of the unselected NAND string.

8. The method of claim 1, wherein:

if the selected word line is at the drain-side of the unselected NAND string, the driven voltage on the source line is allowed to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is inversely proportional to a distance of the selected word line from the drain-end of the unselected NAND string.

9. The method of claim 1, wherein:

if the selected word line is at the source-side of the unselected NAND string, a magnitude of the driven voltage on the bit line when the driven voltage on the bit line is allowed to reach the channel of the unselected NAND string is proportional to a distance of the selected word line from the source-end of the unselected NAND string.

10. The method of claim 1, wherein:

if the selected word line is at the drain-side of the unselected NAND string, a magnitude of the driven voltage on the source line when the driven voltage on the source line is allowed to reach the channel of the unselected NAND string is proportional to a distance of the selected word line from the drain-end of the unselected NAND string.

11. The method of claim 1, wherein:

the multiple word lines comprise different adjacent subsets of word lines;

the selected word line is in one of the subsets of word lines; and

if the selected word line is at the source-side of the unselected NAND string, the driven voltage on the bit line is allowed to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is a function of a position of the one of the subsets among the different adjacent subsets.

12. The method of claim 1, wherein:

the multiple word lines comprise different adjacent subsets of word lines;

the selected word line is in one of the subsets of word lines; and

if the selected word line is at the source-side of the unselected NAND string, a magnitude of the driven voltage on the bit line when the driven voltage on the bit line is allowed to reach the channel of the unselected NAND string is set as a function of a position of the one of the subsets among the different adjacent subsets.

13. The method of claim 1, wherein:

the multiple word lines comprise different adjacent subsets of word lines;

the selected word line is in one of the subsets of word lines; and

if the selected word line is at the drain-side of the unselected NAND string, the driven voltage on the source line is allowed to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is a function of a position of the one of the subsets among the different adjacent subsets.

14. The method of claim 1, wherein:

the multiple word lines comprise different adjacent subsets of word lines;

the selected word line is in one of the subsets of word lines; and

if the selected word line is at the drain-side of the unselected NAND string, a magnitude of the driven voltage on the source line when the driven voltage on the source line is allowed to reach the channel of the unselected NAND string is set as a function of a position of the one of the subsets among the different adjacent subsets.

15. A memory controller, comprising:

a storage device comprising a set of instructions, the set of instructions comprising;

instructions to apply an increasing voltage to unselected memory cells in unselected word lines of a memory device in connection with a sensing operation involving a selected memory cell in a selected word line of the memory device, wherein the selected memory cell is in a selected NAND string of the memory device, unselected memory cells are in an unselected NAND string of the memory device, the unselected NAND string comprising a drain-end select gate at a drain-end of the unselected NAND string and a source-end select gate at a source-end of the unselected NAND string;

instructions to, —

if the selected word line is at a source-side of the unselected NAND string, control the drain-end select gate of the unselected NAND string to, at different times during the applying of the increasing voltage, allow a driven voltage on a bit line to reach a channel of the unselected NAND string by providing the drain-end select gate in a conductive state and prevent the driven voltage on the bit line from reaching the channel of the unselected NAND string by providing the drain-end select gate in a non-conductive state;

instructions to, if the selected word line is at a drain-side of the unselected NAND string, control the source-end select gate of the unselected NAND string to, at different times during the applying of the increasing voltage, allow a driven voltage on a source line to reach the channel of the unselected NAND string by providing the source-end select gate in a conductive state and prevent the driven voltage on the source line from reaching the channel of the unselected NAND string by providing the source-end select gate in a non-conductive state;

instructions to, if the selected word line is midrange between the drain-end of the unselected NAND string and the source-end of the unselected NAND string, prevent the driven voltage on the bit line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage by providing the drain-end select gate of the unselected NAND string in a non-conductive state, and preventing the driven voltage on the source line from reaching the channel of the unselected NAND string throughout the applying of the increasing voltage by providing the source-end select gate of the unselected NAND string in a non-conductive state; and

instructions to sense a current in the selected NAND string via the bit line while a boosting voltage is set in the channel of the unselected NAND string; and

a processor operable to execute the set of instructions.

16. The memory controller of claim 15, wherein the set of instructions further comprises:

instructions to allow the driven voltage on the bit line to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is inversely proportional to a distance of the selected word line from the source-end of the unselected NAND string, if the selected word line is at the source-side of the unselected NAND string.

17. The memory controller of claim 15, wherein the set of instructions further comprises:

instructions to allow the driven voltage on the source line to reach the channel of the unselected NAND string for a duration during the applying of the increasing voltage which is inversely proportional to a distance of the selected word line from the drain-end of the unselected NAND string, if the selected word line is at the drain-side of the unselected NAND string.

18. A 3D stacked non-volatile memory device, comprising:

multiple word lines of memory cells including a selected word line and unselected word lines;

an unselected NAND string comprising a drain-end select gate at a drain-end of the unselected NAND string and a source-end select gate at a source-end of the unselected NAND string;

a selected NAND string comprising a drain-end select gate at a drain-end of the selected NAND string and a source-end select gate at a source-end of the selected NAND string;

a selected memory cell connected to the selected word line, the selected memory cells is in the selected NAND string;

unselected memory cells connected to the unselected word line, the unselected memory cells are in the selected NAND string and in the unselected NAND string;

a bit line which is connected to the drain-end of the selected NAND string and the drain-end of the unselected NAND string; and

a control circuit, the control circuit is configured to;

apply an increasing voltage to the unselected memory cells via the unselected word lines in connection with a sensing operation involving the selected memory cell;

during one portion of a time period in which the increasing voltage occurs, provide the drain-end select gate of the unselected NAND string and the source-end select gate of the unselected NAND string in a non-conductive state to float a voltage of a channel of the unselected NAND string;

during another portion of the time period in which the increasing voltage occurs, if the selected word line is at a source-side of the unselected NAND string, provide the drain-end select gate end of the unselected NAND string in a conductive state to connect the channel of the unselected NAND string to a driven voltage on the bit line, wherein the driven voltage on the bit line is connected to the channel of the unselected NAND string for a duration during the time period in which the increasing voltage occurs, and the duration is inversely proportional to a distance of the selected word line from the source-end of the unselected NAND string; and

after the time period, sense a current in the selected NAND string via the bit line.

19. The 3D stacked non-volatile memory device of claim 18, wherein the control circuit is configured to:

during the another portion of the time period in which the increasing voltage occurs, if the selected word line is at a drain-side of the unselected NAND string, control the source-end select gate of the unselected NAND string to connect the channel of the unselected NAND string to a driven voltage on a source line.

20. The 3D stacked non-volatile memory device of claim 19, wherein the control circuit is configured to:

if the selected word line is at the drain-side of the unselected NAND string, connect the driven voltage on the source line to the channel of the unselected NAND string for a duration during the time period in which the increasing voltage occurs, where the duration is inversely proportional to a distance of the selected word line from the drain-end of the unselected NAND string.

21. An apparatus, comprising:

multiple word lines of memory cells including a selected word line and unselected word lines;

an unselected string of the memory cells;

a selected string of the memory cells, the selected string and the unselected strings each comprise a charge-trapping layer and a polysilicon channel layer which extend vertically in a three-dimensional stacked memory structure;

means for performing a boosting phase of the sensing operation, the boosting phase sets a boosting voltage of a channel of an unselected string of the memory cells, the unselected string comprising a drain-end select gate at a drain-end of the unselected string and a source-end select gate at a source-end of the unselected string; and

means for, after the boosting voltage is set, performing a sensing phase of the sensing operation, the sensing phase senses a current in a selected string of the memory cells, the selected NAND string comprising a drain-end select gate at a drain-end of the selected NAND string and a source-end select gate at a source-end of the selected NAND string, wherein during the sensing phase, the current is sensed via a bit line which is connected to the drain-end of the selected string and the drain-end of the unselected string while one or more read voltages are applied to the selected word line;

wherein the means for performing a boosting phase comprises;

means for applying an increasing voltage to the unselected word lines;

means for, if the selected word line is at a source-side of the unselected string, controlling the drain-end select gate of the unselected string to, at different times during the applying of the increasing voltage, allow a driven voltage on the bit line to reach the channel of the unselected string by providing the drain-end select gate of the unselected string in a conductive state and prevent the driven voltage on the bit line from reaching the channel of the unselected string by providing the drain-end select gate of the unselected string in a non-conductive state;

means for, if the selected word line is at a drain-side of the unselected string, controlling the source-end select gate of the unselected string to, at different times during the applying of the increasing voltage, allow a driven voltage on a source line to reach the channel of the unselected string by providing the source-end select gate of the unselected string in a conductive state and prevent the driven voltage on the source line from reaching the channel of the unselected string by providing the source-end select gate of the unselected string in a non-conductive state; and

means for, if the selected word line is midrange between the drain-end of the unselected string and the source-end of the unselected string, preventing the driven voltage on the bit line from reaching the channel of the unselected string throughout the applying of the increasing voltage by providing the drain-end select gate of the unselected string in a non-conductive state throughout the applying of the increasing voltage, and preventing the driven voltage on the source line from reaching the channel of the unselected string, throughout the applying of the increasing voltage by providing the source-end select gate of the unselected string in a non-conductive state.