Shielding technique for semiconductor package including metal lid

• US 9,362,209 B1
• Filed: 01/23/2012
• Issued: 06/07/2016
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Mangrum, Marc Alan
• Primary Examiner(s): Woldegeorgis, Ermias
• Assistant Examiner(s): Liu, Benjamin Tzu-Hung
• Application Number:
  US13/356,349
• Time in Patent Office: 1,597 Days
• Field of Search: 257/670
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/043 the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/1632 : Disposition
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.

Claims

1. A semiconductor package comprising:

a leadframe including a die pad having at least one tie bar connected thereto and extending therefrom and a plurality of leads extending at least partially about the die pad in spaced relation thereto, each lead having a lead top surface and a lead bottom surface;

a semiconductor die having a first surface and a second surface opposed to the first surface, the second surface attached to the die pad and electrically connected to at least some of the leads;

a package body covering at least portions of the die pad, the tie bar and the leads where at least some leads each have both the lead top surface at least partially exposed in a top surface of the package body and the lead bottom surface at least partially exposed in a bottom surface of the package body, the package body including at least one via which is formed therein and terminates on the tie bar, the via being laterally surrounded by the package body, wherein;

the top surface of the package body includes at least first and second sections, the first section being recessed relative to the second section;

the via is formed in the second section of the top surface;

the package body is formed such that the die pad, the tie bar and at least some of the leads each include a portion that is exposed in the first section of the top surface; and

the top surface of the package body is positioned below the first surface of the semiconductor die;

a conductive material within the via and contacting the tie bar; and

a lid attached to the conductive material adjacent to the second section of the top surface of the package body to facilitate the electrical connection of the lid to the tie bar, wherein the tie bar comprises;

a generally planar top surface adjacent the top surface of the package body, and

a generally planar bottom surface disposed in opposed relation to the top surface and covered by the package body.

2. The semiconductor package of claim 1 wherein the semiconductor die is further electrically connected to the die pad, and wherein the package body does not cover the semiconductor die.

3. The semiconductor package of claim 2 wherein the semiconductor die is electrically connected to the die pad and at least some of the leads by conductive wires which are covered by the lid.

4. The semiconductor package of claim 1 wherein the via has a generally circular configuration, and wherein the semiconductor die is electrically connected to the die pad by a conductive wire attached to a terminal on the first surface of the semiconductor die and attached to the die pad so that the terminal, the die pad, the tie bar and the lid are configured to be in electrical communication.

5. The semiconductor package of claim 1, wherein those leads which include a portion exposed in the first section of the top surface of the package body each comprise:

a generally planar top surface which is partially exposed in the first section of the top surface of the package body;

a generally planar bottom surface which is disposed in opposed relation to the top surface and exposed in the bottom surface of the package body; and

a shelf which is disposed in opposed relation to the top surface and recessed relative to the bottom surface, the shelf being covered by the package body.

6. The semiconductor package of claim 5 wherein the die pad comprises:

a generally planar top surface which is exposed in the first section of the top surface of the package body;

a generally planar bottom surface which is disposed in opposed relation to the top surface and exposed in the bottom surface of the package body; and

a shelf which is disposed in opposed relation to the top surface and recessed relative to the bottom surface, the shelf being covered by the package body.

7. The semiconductor package of claim 1, wherein the top surface of the tie bar is partially exposed in the top surface of the package body.

8. The semiconductor package of claim 1 wherein:

the package body is formed to include the at least one via which extends to the tie bar and is laterally surrounded by the package body, and at least one via which extends to a corresponding one of the leads and is laterally surrounded by the package body; and

the vias are filled with the conductive material to facilitate the electrical connection of the lid to the tie bar and to at least one of the leads.

9. A semiconductor package comprising:

a leadframe within a package body, the leadframe comprising a die pad and a plurality of leads extending at least partially about the die pad, each lead having a first surface and an opposing second surface;

a semiconductor die having a first major surface and a second major surface opposed to the first major surface, the second major surface attached to the die pad and electrically connected to at least some of the leads;

the package body covering at least portions of the leads where at least some leads each have both the first surface at least partially exposed in a top surface of the package body and the second surface at least partially exposed in bottom surface of the package body, the package body including at least one via which is formed therein and extends to a corresponding one of the leads, the via laterally surrounded by the package body;

a conductive material within the via and contacting the corresponding one of the leads; and

a lid attached to the conductive material to facilitate electrical connection of the lid to the corresponding one of the leads, wherein;

the package body includes a bottom surface, and a top surface having at least first and second sections, the first section being recessed relative to the second section;

the via is in the second section of the top surface;

the lid is attached to the second section of the top surface; and

the die pad and at least some of the leads each include a portion exposed in the first section of the top surface.

10. The semiconductor package of claim 9 wherein the semiconductor die is further electrically connected to the die pad by a conductive wire attached to a terminal on the first surface of the semiconductor die and the die pad.

11. The semiconductor package of claim 10 wherein the semiconductor die is electrically connected to the die pad and at least some of the leads by conductive wires which are covered by the lid, and wherein the first portion of the package body isolates at least some of the leads from the lid.

12. The semiconductor package of claim 9 wherein the via has a generally circular configuration.

13. The semiconductor package of claim 9, wherein those leads which include a portion exposed in the first section of the top surface of the package body each comprise:

a generally planar top surface which is partially exposed in the first section of the top surface of the package body;

a generally planar bottom surface which is disposed in opposed relation to the top surface and exposed in the bottom surface of the package body; and

a shelf which is disposed in opposed relation to the top surface and recessed relative to the bottom surface, the shelf being covered by the package body.

14. The semiconductor package of claim 13 wherein the die pad comprises:

a generally planar top surface which is exposed in the first section of the top surface of the package body;

a generally planar bottom surface which is disposed in opposed relation to the top surface and exposed in the bottom surface of the package body; and

a shelf which is disposed in opposed relation to the top surface and recessed relative to the bottom surface, the shelf being covered by the package body.

15. A semiconductor package comprising:

a die pad;

a semiconductor die attached to the die pad;

a plurality of leads extending at least partially about the die pad in spaced relation thereto, the semiconductor die being electrically connected to at least some of the leads, wherein each of the leads has a recessed top surface, a non-recessed top surface, a recessed bottom surface and a non-recessed bottom surface;

a package body covering at least portions of the die pad and the leads, the package body including a bottom surface, and a top surface having at least first and second sections, the first section being recessed relative to the second section, with a portion of the non-recessed top surface of at least one of the leads being exposed in the second section and portions of the recessed top surfaces of at least some of the leads being exposed in the first section; and

a lid attached to the second section of the top surface of the package body by a conductive material and further attached to the non-recessed top surface of at least one of the leads exposed in the second section by the conductive material such that lid is electrically connected to the non-recessed top surface of at least one of the leads.

16. The semiconductor package of claim 15, wherein the semiconductor die is electrically connected to the die pad and at least some of the leads by conductive wires which are covered by the lid, and wherein at least some of the leads have inner end portions angularly offset relative to a remaining portion thereof.

17. The semiconductor package of claim 15 wherein:

the package body covers the recessed bottom surfaces of each of the leads; and

the non-recessed bottom surfaces of each of the leads are exposed in the bottom surface of the insulative package body.

18. The semiconductor package of claim 17 wherein the die pad comprises:

a generally planar top surface which is exposed in the first section of the top surface of the package body;

a generally planar bottom surface which is disposed in opposed relation to the top surface and exposed in the bottom surface of the package body; and

a shelf which is disposed in opposed relation to the top surface and recessed relative to the bottom surface, the shelf being covered by the package body.