Integrated circuit devices and methods

• US 9,362,291 B1
• Filed: 08/09/2014
• Issued: 06/07/2016
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Thummalapally, Damodar R., Clark, Lawrence T., Thompson, Scott E., Roy, Richard S., Rogenmoser, Robert
• Primary Examiner(s): Dinh, Son
• Application Number:
  US14/455,892
• Time in Patent Office: 668 Days
• Field of Search: 365/154, 365/189.11, 365/189.14
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.

Claims

1. An integrated circuit comprising:

multiple static random access memory (SRAM) cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate;

at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and

a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.

2. The integrated circuit of claim 1 wherein the bias voltage is a source bias.

3. The integrated circuit of claim 1, wherein the bias voltage is a dynamic bias.

4. The integrated circuit of claim 1, further comprising:

a power supply line connected to the sources of the two pull-up transistors of each SRAM to apply a power supply thereto, the power supply line applying a boosted power supply voltage to the pull-up transistors for one or more selected SRAM cells, wherein enhanced body coefficient of the pull-up transistors increases a read static noise margin of the selected SRAM cell when the boosted power supply voltage is applied to the pull-up transistors.

5. The integrated circuit of claim 1, wherein the bias voltage is a forward body bias voltage that is applied to the screening region of the pull-up transistors, the forward 5 body bias voltage being applied during a read operation to increase the read static noise margin of the SRAM cell.

6. The integrated circuit of claim 5, wherein the applied forward body bias voltage 10 provides a predetermined read static noise margin for the SRAM cell.

7. The integrated circuit of claim 1, wherein the bias voltage is a reverse body bias voltage that is applied to the screening region of the pull-up transistors, the reverse body bias voltage being applied during a write operation to increase the write margin of 15 the SRAM cell.

8. The integrated circuit of claim 7, wherein the applied reverse body bias voltage provides a predetermined write margin for the SRAM cell.

9. The integrated circuit of claim 1, wherein the enhanced body coefficient provides a predetermined write margin for the SRAM cell.

10. The integrated circuit of claim 9, wherein the enhanced body coefficient provides 25 a predetermined write margin for the SRAM cell, wherein the write margin is less than the read static noise margin.

11. The integrated circuit of claim 1, further comprising:

a plurality of SRAM cell groups, each group having a plurality of SRAM cells;

at least one body bias control circuit to generate a body bias control signal for each group, the body bias control signal of a first group transitioning from an inactive level to an active level in response to a first received memory address selecting at least one SRAM cell in the first group; and

a body bias network for each group, the body bias network being operable to apply a first body bias voltage to the screening regions of the SRAM cells of the first group if the corresponding body bias control signal is at an inactive level, the biasing network being further operable to apply a second body bias voltage to the screening regions of the SRAM cells of the first group if the corresponding 10 body bias control signal is at an active level, the biasing network being operable to apply the first and second body bias voltage to the SRAM cells in the first group and not an adjacent group.

12. The integrated circuit of claim 11, further including:

a plurality of word lines for each group, at least a first word line of the plurality of word lines transitioning from an inactive level to an active level in response to the first received memory address selecting at least a first row of SRAM cells in the first group, wherein the first word line transitions to the active level at least a first predetermined duration of time after the body bias control 20 signal transitions to the active level.

13. The integrated circuit of claim 11, further comprising:

a standard decode section operable to drive the first word line to the active level if the received first memory address selects the SRAM cell 25 in the first group of memory cells; and

a body bias decode section generating a plurality of body bias control signals in response to the first received memory address, each body bias control signal corresponding to a group of memory cells, the body bias decode section being operable to drive the body bias control 30 signal of the first group to the active level if the received first memory address selects at least one SRAM cell in the first group,

wherein the body bias decode section drives the body bias control signal of the first group at least a first predetermined duration of time before the standard decode section drives the first word line to the active level.

14. The integrated circuit of claim 10, further comprising:

the first word line transitioning from the active level to the inactive level in response to a second received memory address not selecting the first row of SRAM cells; and

the body bias select signal of the first group transitioning from the active 10 level to the inactive level in response to the received second memory address not selecting at least one SRAM cell in the first group,

wherein the body bias select signal of the first group transitions to the inactive level after at least a second predetermined duration of time following the first word line transitioning to the inactive level.

15. The integrated circuit of claim 1, further comprising:

a plurality of SRAM cell groups, each group having a plurality of SRAM cells;

at least one source bias control circuit to generate source bias control 20 signals for each group, the source bias control signal of a first group transitioning from an inactive level to an active level in response to a first received memory address selecting at least one SRAM cell in the first group; and

a source bias network for each group, the source bias network being operable to apply a first source bias voltage to the SRAM cells of the first group if 25 the corresponding source bias control signal is at an inactive level, the source bias network being further operable to apply a second source bias voltage to the SRAM cells of the first group if the corresponding source bias control signal is at an active level, the source bias network being operable to apply the first and second source bias voltage to the SRAM cells in the first group and not an 30 adjacent group.

16. The integrated circuit of claim 15, further including:

a plurality of word lines for each group, at least a first word line of the plurality of word lines transitioning from an inactive level to an active level in response to the first received memory address selecting at least a first row of 5 SRAM cells in the first group, wherein the first word line transitions to the active level at least a third predetermined duration of time after the source bias control signal transitions to the active level.

17. The integrated circuit of claim 16, further comprising:

a standard decode section operable to drive the first word line to the active level if the received first memory address selects the SRAM cell in the first group of memory cells; and

a source bias decode section generating a plurality of source bias control signals in response to the first received memory address, each 15 source bias control signal of the plurality of source bias control signals corresponding to a group of memory cells, the source bias decode section being operable to drive the source bias control signal of the first group to the active level if the received first memory address selects at least one SRAM cell in the first group,

wherein the source bias decode section drives the source bias control signal of the first group at least a third predetermined duration of time before the standard decode section drives the first word line to the active level.

18. The integrated circuit of claim 17, further comprising:

the first word line transitioning from the active level to the inactive level in response to a second received memory address not selecting the first row of SRAM cells; and

the source bias select signal of the first group transitioning from the active 30 level to the inactive level in response to the received second memory address not selecting at least one SRAM cell in the first group,

wherein the source bias select signal of the first group transitions to the inactive level after at least a fourth predetermined duration of time following the first word line transitioning to the inactive level.

19. The integrated circuit of claim 1, wherein:

the pull-up transistors, the pull-down transistors, and the pass-gate transistors lack halo implant regions near the transistor source and drain that extend into the channel.