Organic light-emitting diode (OLED) display

• US 9,362,347 B2
• Filed: 12/22/2014
• Issued: 06/07/2016
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yoon, Ju-Won, Lee, Il-Jeong, Im, Choong-Youl
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US14/578,844
• Publication Number:
  US 20150372070A1
• Time in Patent Office: 533 Days
• Field of Search: 257/40, 257/59, 257/65, 257/88, 257/211, 257/E29.003, 257/E29.117, 257/E29.273, 257/E27.111, 257/E51.018, 257/E21.09, 365/117, 365/189.15, 438/23, 438/29, 438/151, 438/157, 438/488
• US Class Current: 1/1
• CPC Class Codes: H10K 50/11 characterised by the electroluminescent [EL] layers
• CPC Class Codes: H10K 50/81 Anodes
• CPC Class Codes: H10K 50/82 Cathodes
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/805 Electrodes

Abstract

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels. Each of the pixels includes a first insulating layer and first and second signal lines spaced apart from each other. At least a portion of the first and second signal lines is formed over the first insulating layer. Each pixel also includes a second insulating layer interposed between the first and second signal lines. The second insulating layer has a lower permittivity that the first insulating layer.

Claims

1. An organic light-emitting diode (OLED) display, comprising:

a plurality of pixels, wherein each of the pixels comprises;

a first insulating layer;

a first signal line configured to transmit a first signal to the pixel;

a second signal line spaced apart from the first signal line and formed on the same layer as the first signal line, wherein the second signal line is configured to transmit a second signal to the pixel and wherein at least a portion of the first and second signal lines is formed over the first insulating layer; and

a second insulating layer interposed between the first and second signal lines, wherein the second insulating layer has a lower permittivity than the first insulating layer,

wherein the second insulating layer is interposed between portions of the first insulating layer.

2. The OLED display of claim 1, wherein the first insulating layer is formed of an inorganic material and wherein the second insulating layer is formed of an organic material.

3. The OLED display of claim 1, wherein each pixel further comprises a planarization layer covering the first and second signal lines and formed of the same material as the second insulating layer.

4. The OLED display of claim 1, wherein each pixel further comprises an etch stop layer formed below the second insulating layer and wherein the etch stop layer has an etching rate that is different from that of the first insulating layer.

5. The OLED display of claim 1, further comprising a substrate, wherein each pixel further comprises a driving thin film transistor (TFT) formed over the substrate, wherein the first signal line is a data line configured to transmit a data signal to the pixel, and wherein the second signal line is a contact metal electrically connected to the driving TFT via a contact hole.

6. The OLED display of claim 5, wherein the first signal line overlaps at least a portion of the driving TFT and wherein the first insulating layer is interposed between the first signal line and the driving TFT.

7. The OLED display of claim 5, wherein each pixel further comprises a storage capacitor including i) a first electrode connected to a driving gate electrode of the driving TFT and ii) a second electrode formed over and insulated from the first electrode and wherein the driving gate electrode and the first electrode are integrally formed on the same layer.

8. The OLED display of claim 7, wherein each of the driving TFTs comprises a driving semiconductor layer formed below the driving gate electrode and insulated from the driving gate electrode by a first gate insulating layer.

9. The OLED display of claim 8, wherein each of the pixels further comprises an emission control TFT electrically connected between the driving TFT and an OLED, wherein the emission control TFT comprises i) an emission control semiconductor layer formed on the same layer as the driving semiconductor layer and ii) an emission control gate electrode insulated from the emission control semiconductor layer by the first gate insulating layer.

10. The OLED display of claim 9, wherein the OLED comprises i) an anode electrode, ii) a cathode electrode opposing the anode electrode, and iii) an organic emission layer interposed between the anode and cathode electrodes.

11. The OLED display of claim 7, wherein each of the storage capacitors comprises a second gate insulating layer interposed between the first and second electrodes.

12. The OLED display of claim 7, wherein the second electrode of each of the storage capacitors is electrically connected to a driving voltage line configured to transmit a driving voltage.

13. An organic light-emitting diode (OLED) display, comprising:

a substrate; and

a plurality of pixels, wherein each of the pixels comprises;

a driving thin film transistor (TFT) formed over the substrate;

an interlayer insulating layer covering the driving TFT;

a contact metal formed over the interlayer insulating layer and electrically connected to the driving TFT via a contact hole; and

a first signal line formed over the interlayer insulating layer and overlapping at least a portion of the driving TFT,

wherein the interlayer insulating layer comprises i) a first insulating layer formed below the contact metal and the first signal line and ii) a second insulating layer interposed between the contact metal and the first signal line, wherein the second insulating layer has a lower permittivity than the first insulating layer,

wherein the second insulating layer is interposed between portions of the first insulating layer.

14. The OLED display of claim 13, wherein the first insulating layer is formed of an inorganic material and wherein the second insulating layer is formed of an organic material.

15. The OLED display of claim 13, wherein each pixel further comprises a planarization layer covering the contact metal and the first signal line and formed of the same material as the second insulating layer.

16. The OLED display of claim 13, wherein each pixel further comprises an etch stop layer formed below the second insulating layer and wherein the etch stop layer has an etching rate that is different from that of the first insulating layer.

17. The OLED display of claim 13, wherein each pixel further comprises a storage capacitor including i) a first electrode connected to a driving gate electrode of the driving TFT and ii) a second electrode formed over and insulated from the first electrode and wherein the driving gate electrode and the first electrode are integrally formed on the same layer.

18. The OLED display of claim 17, wherein each of the driving TFTs comprises a driving semiconductor layer formed below the driving gate electrode and insulated from the driving gate electrode by a first gate insulating layer, wherein the storage capacitor comprises a second gate insulating layer interposed between the first and second electrodes, and wherein the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.