FETs and methods for forming the same

• US 9,362,386 B2
• Filed: 09/12/2014
• Issued: 06/07/2016
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Fan, Chun-Hsiang, Lee, Tung Ying, Liu, Chi-Wen
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US14/485,405
• Publication Number:
  US 20150001468A1
• Time in Patent Office: 634 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.

Claims

1. A method comprising:

forming a channel region on a substrate, wherein the forming the channel region comprises;

forming a fin on the substrate; and

epitaxially growing a quantum well structure on the fin, the channel region comprising the quantum well structure;

after forming the channel region, re-shaping the channel region to have a major surface portion of a sidewall with a plurality of lattice shift locations in stair-step increments, each of the plurality of lattice shift locations comprising an inward or outward lattice shift relative to a center of the channel region;

forming a dielectric on the major surface portion of the sidewall; and

forming a gate electrode on the dielectric.

2. The method of claim 1, wherein the re-shaping the channel region comprises a wet etch.

3. The method of claim 1, wherein the forming the channel region comprises:

forming a fin on the substrate;

forming a recess in the fin; and

epitaxially growing the channel region in the recess in the fin.

4. The method of claim 3 further comprising after epitaxially growing the channel region, recessing the fin to form a void under the channel region, the forming the dielectric further comprising forming the dielectric in the void.

5. The method of claim 1, wherein the forming the channel region comprises:

epitaxially growing a channel layer on a first source/drain region;

epitaxially growing a second source/drain layer on the channel layer; and

patterning the second source/drain layer and the channel layer into a second source/drain region and the channel region, respectively.

6. The method of claim 1, wherein the re-shaping comprises a mixture of ammonium hydroxide and hydrochloric acid.

7. A method comprising:

forming a channel region of a device on a substrate, the channel region comprising a semiconductor material, the channel region having a first exterior surface shape, wherein the channel region comprises a quantum well;

after forming the channel region, etching the channel region to form a second exterior surface shape different from the first exterior surface shape, wherein the second exterior surface shape comprises a plurality of lattice shift locations in stair-step increments;

forming a gate dielectric on the second exterior surface shape of the channel region; and

forming a gate electrode on the gate dielectric.

8. The method of claim 7, wherein the second exterior surface shape includes a crystalline surface orientation.

9. The method of claim 7, wherein the forming the channel region comprises:

forming a fin on the substrate;

forming a dummy gate on the fin of the substrate;

forming a dielectric over the dummy gate and the fin;

after forming the dielectric, exposing a portion of the fin by removing the dummy gate;

etching the exposed portion of the fin; and

epitaxially growing the semiconductor material of the channel region on a remaining portion of the fin.

10. The method of claim 9 further comprising etching an underlying portion of the fin underlying the channel region, the gate dielectric and the gate electrode being formed fully around the channel region.

11. The method of claim 7, wherein the forming the channel region comprises:

forming a fin on a substrate; and

epitaxially growing the semiconductor material of the channel region on the fin.

12. The method of claim 11 further comprising forming a dielectric layer over the semiconductor material of the channel region, the etching the channel region being performed after the forming the dielectric layer.

13. The method of claim 7, wherein the forming the channel region comprises forming a vertical channel structure, the gate dielectric and gate electrode being fully around the vertical channel structure, a first source/drain region being in the vertical channel structure and proximate the substrate, a second source/drain region being in the vertical channel structure and distal from the substrate.

14. A method comprising:

forming a device structure on a substrate, the device structure comprising a first source/drain region, a second source/drain region, and a channel region disposed between the first source/drain region and the second source/drain region;

forming a dielectric layer on the first source/drain region;

after forming the dielectric layer, re-shaping the channel region using an etching process;

forming a gate dielectric on the re-shaped channel region;

forming a gate electrode on the gate dielectric;

forming a fin on the substrate;

forming the first source/drain region and the second source/drain region in the fin, an intermediate fin portion of the fin being disposed between the first source/drain region and the second source/drain region;

after forming the dielectric layer, exposing the intermediate fin portion of the fin;

after exposing the intermediate fin portion, recessing the intermediate fin portion to form a V-shaped recess;

epitaxially growing the channel region in the recess; and

etching a portion of the fin under the channel region to form a void, wherein the gate dielectric and the gate electrode are formed in the void.

15. The method of claim 14, wherein the forming the device structure comprises:

forming a fin on the substrate;

epitaxially growing the channel region on the fin; and

forming the first source/drain region and the second source/drain region in the fin.

16. The method of claim 15, wherein the channel region comprises a quantum well.

17. The method of claim 14, wherein the forming the device structure comprises forming a vertical channel structure on the substrate, the first source/drain region being in the vertical channel structure proximate the substrate, the second source/drain region being in the vertical channel structure distal from the substrate.