Signal envelope processing

• US 9,362,875 B2
• Filed: 07/02/2014
• Issued: 06/07/2016
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Blyth, Malcolm, Mackay, Graeme Gordon
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US14/322,747
• Publication Number:
  US 20150008962A1
• Time in Patent Office: 706 Days
• Field of Search: 327/58, 327/59, 327/62
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 3/183 with semiconductor devices only
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

Methods and apparatus for detection and tracking of a signal envelope. The circuit comprises absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples. An envelope tracker maintains an envelope output value and compares the first value to the current envelope output value and modifies the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics. The absolute value circuitry has a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs the first value based on the magnitudes of the samples received at the first input and the samples received at the second input. Using the first digital signal provides an early indication of any increases in signal envelope whereas the second digital signal can allow a more accurate estimation.

Claims

1. An envelope detection circuit comprising:

absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples; and

an envelope tracker configured to maintain an envelope output value and to compare the first value to the current envelope output value and modify the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics;

wherein the absolute value circuitry comprises a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and is configured to output said first value based on the magnitudes of the samples received at the first input and the samples received at the second input.

2. An envelope detection circuitry as claimed in claim 1 wherein the envelope tracker comprises:

attack circuitry for increasing the envelope output value; and

decay circuitry for decreasing the envelope output value;

wherein the attack circuitry operates in response to a first clock signal and the decay circuitry operates in response to a frame clock signal which has a rate slower than the first clock signal.

3. An envelope detection circuit as claimed in claim 2 wherein the attack circuitry is configured to compare the first value to the envelope output value to determine whether the envelope output value should be increased and, if so, to increase the envelope output value to correspond to the first value.

4. An envelope detection circuit as claimed in claim 2 wherein the decay circuitry is configured to determine if the first value was lower than the envelope output value for a predetermined number of successive frame periods defined by the frame clock signal and, if so, to decrease the envelope output value.

5. An envelope detection circuit as claimed in claim 2 wherein the frame period is equal to the period between successive samples at the first sample rate.

6. An envelope detection circuit as claimed in claim 2 wherein said absolute value circuitry comprises a maximum value detector configured to receive samples from both said first input and said second input and maintain said first value corresponding to the maximum magnitude value of any sample received within a frame period defined by said frame clock signal.

7. An envelope detection circuit as claimed in claim 6 wherein the maximum value detector is configured such that the first value is updated at any time in a frame period if a sample with a value greater than the current first value is received during the frame period.

8. An envelope detection circuit as claimed in claim 7 wherein the attack circuitry is configured such that the envelope output value may be updated at any time if the first value increases to a value greater than the current envelope output value during the frame period.

9. An envelope detection circuit as claimed in claim 6 wherein the decay circuitry is configured to compare the first value at the end of a frame period to the envelope output value so as to detect if the first value was lower than the envelope output value for that frame period.

10. An envelope detection circuit as claimed in claim 9 wherein the decay circuitry is configured such that the envelope output value is only decreased if the first value is lower than the envelope output value by a predetermined amount for said predetermined number of successive frame periods.

11. An envelope detection circuit as claimed in claim 2 wherein the attack circuitry is configured to detect if the first value is greater than or equal to the envelope output value and, if so, output a first control signal and the decay circuitry is responsive to said first control signal to determine if the first value was lower than the envelope output value for that frame period.

12. An envelope detection circuit as claimed in claim 2 wherein the decay circuitry is configured to compare the envelope output value at the end of a frame period to a held envelope value corresponding to the envelope output value at the start of that frame period so as to detect if the first value was lower than the envelope output value for that frame period.

13. An envelope detection circuit as claimed in claim 9 wherein the decay circuitry comprises hold circuitry, the hold circuitry comprising a counter configured to count the number of successive frame periods in which the first value was lower than the envelope output value, wherein the counter is reset to a starting value following or during any frame period in which the frame maximum value is not lower than the envelope output value.

14. An envelope detection circuit as claimed in claim 13 wherein the decay circuitry comprises decrement circuitry configured to decrease the value of the envelope output value by a predetermined amount if said counter has reached a specified count value.

15. An envelope detection circuit as claimed in claim 1 wherein the absolute value circuitry comprises a multiplexor having inputs coupled to said first and second inputs and configured to produce a data stream consisting of samples received from the first input interspersed with samples received from said second input.

16. A signal processing circuit comprising:

an envelope detection circuit as claimed in claim 1;

a first signal path input for receiving the first digital signal;

a first interpolator configured to interpolate the first digital signal to generate a second digital signal at the second sample rate;

a digital-to-analogue converter configured to receive a digital signal based on the second digital signal and generate a first analogue signal; and

an amplifier configured to amplify the first analogue signal;

wherein the first input of the envelope detection circuit is configured to receive the first digital signal and the second input of the envelope detector is configured to receive the second digital signal.

17. A signal processing circuit as claimed in claim 15 further comprising a power controller for controlling the power supply to at least one of the digital-to-analogue converter and the amplifier based on the envelope output value.

18. A signal processing circuit as claimed in claim 15 comprising:

a digital variable gain element for applying a digital gain to the signal received by the digital-to-analogue converter;

an analogue variable gain element for applying an analogue gain to the first analogue signal produced by the digital-to-analogue converter; and

a gain controller for controlling the allocation of gain between the digital variable gain element and the analogue variable gain element based on the envelope output value.

19. An electronic device comprising an envelope detection circuit as claimed in claim 1 wherein said device is at least one of:

an audio device;

a portable device;

a communications device;

a computing device;

a battery powered device;

an audio player;

a video player;

a gaming device;

a mobile telephone;

a laptop, notebook or tablet computer.

20. A method of envelop detection comprising:

receiving input data samples at absolute value circuitry and outputting a first value corresponding to the magnitude of said data samples;

maintaining an envelope output value; and

comparing the first value to the current envelope output value and modifying the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics;

wherein the absolute value circuitry receives a first digital signal at a first sample rate and also an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs said first value based on the magnitudes of the samples of first digital signal and the interpolated version of the first digital signal.