Sorting decoder

• US 9,362,947 B2
• Filed: 08/11/2015
• Issued: 06/07/2016
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Cronie, Harm, Holden, Brian
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US14/823,866
• Publication Number:
  US 20160036461A1
• Time in Patent Office: 301 Days
• Field of Search: 341/155, 341/158, 341/159, 341/160
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: H03M 1/18 Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
• CPC Class Codes: H03M 7/00 Conversion of a code where information is represented by a given sequence or number of digits to a code where the same , similar or subset of information is represented by a different sequence or number of digits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Claims

1. A sorting decoder comprising:

a dynamic reference generator configured to generate a monotonic dynamic reference signal;

a set of n comparators, each comparator configured to operate on (i) a respective input signal of a set of n input signals and (ii) the monotonic dynamic reference signal, the set of n comparators configured to form a set of n comparator outputs;

a first logic circuit configured to detect when N comparator outputs of the set of n comparator outputs have a low state and n-N remaining comparator outputs have a high state and output a first latching signal, the N comparator outputs corresponding to a set of N most positive input signals, wherein 1≦

N<

n;

a first latch configured to latch a first snapshot of n comparator outputs from the set of n comparators based on the first latching signal;

a second logic circuit configured to detect when M comparator outputs of the set of n comparator outputs have a high state and n-M remaining comparator outputs have a low state and output a second latching signal, the M comparator outputs corresponding to a set of M most negative input signals, wherein 1≦

M<

n; and

,

a second latch configured to latch a second snapshot of n comparator outputs from the set of n comparators based on the second latching signal.

2. The sorting circuit of claim 1, further comprising a decoder configured to generate a codeword based on the first and second snapshots of n comparator outputs.

3. The sorting circuit of claim 1, wherein the first and second logic circuits comprise glitchless counters to detect the N most positive input signals and the M most negative n input signals.

4. The sorting circuit of claim 3, wherein a delay of the glitchless counters is balanced by a delay element.

5. The sorting circuit of claim 1, wherein the monotonic dynamic reference signal corresponds to a voltage sweep in a positive-to-negative direction.

6. The sorting circuit of claim 1, wherein the monotonic dynamic reference signal corresponds to a voltage sweep is in a negative-to-positive direction.

7. The sorting circuit of claim 1, wherein the monotonic dynamic reference signal corresponds to voltage sweeps in midpoint-to-extreme directions.

8. The sorting circuit of claim 1, wherein the monotonic dynamic reference signal corresponds to voltage sweeps in extreme-to-midpoint directions.

9. The sorting circuit of claim 1, wherein a high state corresponds to a logic ‘

1’ and

a low state corresponds to a logic ‘

0’

.

10. The sorting circuit of claim 3, wherein the glitchless counters comprise AND and OR gates.

11. A method comprising:

generating, using a dynamic reference generator, a monotonic dynamic reference signal;

forming a set of n comparator outputs by operating on (i) a respective input signal of a set of n input signals and (ii) the monotonic dynamic reference signal;

detecting when a set of N comparator outputs have a low state and n-N comparators have a low state, and responsively generating a first latching signal, the N comparator outputs corresponding to a set of N most positive input signals, wherein 1≦

N<

n;

latching a first snapshot of n comparator outputs based on the first latching signal;

detecting when a set of M comparator outputs have a high state and n-M comparator outputs have a low state, and responsively generating a second latching signal, the M comparator outputs corresponding to a set of M most negative input signals, wherein 1≦

M<

n; and

,

latching a second snapshot of n comparator outputs based on the second latching signal.

12. The method of claim 11, further comprising forming a codeword by decoding the first and second snapshots of n comparator outputs.

13. The method of claim 11, wherein the N most positive input signals and the M most negative n input signals are detected using glitchless counters.

14. The method of claim 13, wherein a delay of the glitchless counters is balanced by a delay element.

15. The method of claim 11, wherein the monotonic dynamic reference signal corresponds to a voltage sweep in a positive-to-negative direction.

16. The method of claim 11, wherein the monotonic dynamic reference signal corresponds to a voltage sweep is in a negative-to-positive direction.

17. The method of claim 11, wherein the monotonic dynamic reference signal corresponds to voltage sweeps in midpoint-to-extreme directions.

18. The method of claim 11, wherein the monotonic dynamic reference signal corresponds to voltage sweeps in extreme-to-midpoint directions.

19. The method of claim 11, wherein a high state corresponds to a logic ‘

1’ and

wherein a low state corresponds to a logic ‘

0’

.

20. The method of claim 13, wherein the glitchless counters comprise AND and OR gates.