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Sorting decoder

  • US 9,362,947 B2
  • Filed: 08/11/2015
  • Issued: 06/07/2016
  • Est. Priority Date: 12/30/2010
  • Status: Active Grant
First Claim
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1. A sorting decoder comprising:

  • a dynamic reference generator configured to generate a monotonic dynamic reference signal;

    a set of n comparators, each comparator configured to operate on (i) a respective input signal of a set of n input signals and (ii) the monotonic dynamic reference signal, the set of n comparators configured to form a set of n comparator outputs;

    a first logic circuit configured to detect when N comparator outputs of the set of n comparator outputs have a low state and n-N remaining comparator outputs have a high state and output a first latching signal, the N comparator outputs corresponding to a set of N most positive input signals, wherein 1≦

    N<

    n;

    a first latch configured to latch a first snapshot of n comparator outputs from the set of n comparators based on the first latching signal;

    a second logic circuit configured to detect when M comparator outputs of the set of n comparator outputs have a high state and n-M remaining comparator outputs have a low state and output a second latching signal, the M comparator outputs corresponding to a set of M most negative input signals, wherein 1≦

    M<

    n; and

    ,a second latch configured to latch a second snapshot of n comparator outputs from the set of n comparators based on the second latching signal.

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