Methods and systems for high bandwidth chip-to-chip communications interface

• US 9,362,974 B2
• Filed: 08/11/2015
• Issued: 06/07/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Fox, John, Holden, Brian, Hunt, Peter, Keay, John D., Shokrollahi, Amin, Stewart, Andrew Kevin John, Surace, Giuseppe, Ulrich, Roger, Simpson, Richard
• Primary Examiner(s): ODOM, CURTIS B
• Application Number:
  US14/823,870
• Publication Number:
  US 20150349835A1
• Time in Patent Office: 301 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Claims

1. An apparatus comprising:

a multi-wire bus configured to receive a set of N signals corresponding to N elements of a code word, wherein the elements of the code word comprise a set of at least three values, wherein the code word represents a set of n input bits, wherein n is an integer greater than 1 and N<

2n;

a reference-less line receiver comprising a set of n+1 comparators, the set of n+1 comparators configured to operate on the received set of signals and responsively form a set of n+1 comparator outputs based on the received signals, wherein at least two comparators receive a common signal of the received set of N signals; and

,

a decoder configured to receive the set of n+1 comparator outputs and responsively generate a set of n output bits representing the set of n input bits.

2. The apparatus of claim 1, wherein 5 comparator outputs are decoded to generate 5 output bits.

3. The apparatus of claim 1, wherein the code word is balanced.

4. The apparatus of claim 3, wherein the set of at least three values comprises the set of values consisting of {−

1, 0, +1}.

5. The apparatus of claim 1, wherein each value of each element of the code word corresponds to a voltage that is less than a voltage Vdd supplied by a power source.

6. The apparatus of claim 5, wherein at least one element corresponds to a voltage of ½

*Vdd.

7. The apparatus of claim 5, wherein at least one element corresponds to a voltage of ¼

*Vdd.

8. The apparatus of claim 1, wherein 4 comparator outputs are decoded to generate 3 output bits.

9. The apparatus of claim 1, wherein each received signal is terminated to a termination voltage Vt using a termination resistor.

10. The apparatus of claim 9, wherein Vt corresponds to system ground.

11. The apparatus of claim 1, wherein each received signal is terminated to a common node using a termination resistor.

12. The apparatus of claim 1, wherein the decoder comprises combinatorial logic to decode the set of n comparator outputs.

13. The apparatus of claim 1, further comprising:

a plurality of wires configured to receive the set of n input bits representing the set of n output bits;

an encoder configured to generate the elements of the code word; and

,

a transmit driver configured to transmit each respective element of the code word on a respective output wire of a set of output wires.

14. The apparatus of claim 13, wherein for each respective element of the code word to be transmitted, the transmit driver comprises:

a voltage source configured to provide a signal level corresponding to a middle signal level on the respective output wire of the set of output wires;

a first transistor configured to receive a first input signal of a respective pair of input signals, the respective pair of input signals corresponding to a value of the respective element of the code word, wherein the first transistor is configured to provide a positive signal level to the output wire if the first input signal is high and provides no contribution otherwise; and

,

a second transistor configured to receive a second input signal of the respective pair of input signals and provide a negative signal level to the output wire if the second input signal is high and no contribution if otherwise, wherein only one input signal of the respective pair of input signals can be high at one time.

15. The method of claim 14, wherein the middle signal level corresponds to a quiescent signal level.

16. A method comprising:

receiving a set of N signals corresponding to N elements of a code word, the elements of the code word comprising a set of at least three values, the code word representing a set of n input bits, wherein n is an integer greater than 1 and N<

2n;

operating on the N received signals using a set of n+1 comparators and responsively forming a set of n+1 comparator outputs based on the received signals, wherein at least two comparators receive a common signal of the received set of N signals; and

,

decoding the set of n+1 comparator outputs into a set of n output bits representing the n input bits.

17. The method of claim 16, wherein decoding the set of n+1 comparator outputs comprises using a combinatorial logic decoder.

18. A method comprising:

receiving a set of n input bits representing information, wherein n is an integer greater than 1;

generating elements of a code word based on the received set of n input bits; and

, for each element of the code word;

forming a respective pair of driver signals corresponding to a value of a respective element of the code word, wherein at most one driver signal of the respective pair can be high at any time; and

,

generating a signal level on a respective output wire of a set of output wires based on the respective pair of driver signals.

19. The method of claim 18, wherein each driver signal of each respective pair of driver signals controls a respective transistor of a pair of transistors to provide a positive or negative signal level to the respective output wire.

20. The method of claim 19, wherein the positive or negative signal level is contributed by sourcing or sinking current, respectively.